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    CIRCUITRY AND METHOD
    1.
    发明申请
    CIRCUITRY AND METHOD 有权

    公开(公告)号：US20220398970A1

    公开(公告)日：2022-12-15

    申请号：US17806194

    申请日：2022-06-09

    Applicant: Arm Limited

    Inventor： Parameshwarappa Anand Kumar SAVANTH ,  Jedrzej KUFEL ,  Benoit LABBE ,  Sahan Sajeewa Hiniduma Udugama GAMAGE

    IPC: G09G3/20 ,  H02S40/38 ,  H02S50/00

    Abstract: Circuitry comprises driver circuitry to control display of a prevailing display image by display elements of a display device, the driver circuitry generating a signal providing electrical charge for storage by display elements, in which an electrical charge stored by a display element controls a display output of that display element; detector circuitry to detect, for a display image transition from a current display image to a second, display image, a first set of one or more display elements which are in a respective first state controlled by a first stored electrical charge in the current display image and which are required to be in a respective second state controlled by a second electrical charge, in the second display image; switching circuitry, responsive to the detector circuitry, to divert electrical charge from the set of display elements to secondary charge store in response to initiation of the display image transition.

    CONTROLLING VOLTAGE GENERATION AND VOLTAGE COMPARISON
    3.
    发明申请
    CONTROLLING VOLTAGE GENERATION AND VOLTAGE COMPARISON 有权
    控制电压发生和电压比较

    公开(公告)号：US20140340122A1

    公开(公告)日：2014-11-20

    申请号：US13895624

    申请日：2013-05-16

    Applicant: ARM LIMITED

    Inventor： Parameshwarappa Anand Kumar SAVANTH ,  James Edward MYERS ,  David Walter FLYNN ,  Bal S. SANDHU

    IPC: H02M3/156 ,  G01R19/00

    CPC classification number: H02M3/157 ,  G01R19/0084 ,  H02M3/07 ,  Y02B70/16

    Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

    Abstract translation: 集成电路具有用于响应于时钟脉冲从电源电压产生片上电压的电压产生电路。 时钟控制电路控制时钟脉冲的传输到电压产生电路。 时钟控制电路接收参考电压和包括识别偏移的二进制数值的数字偏移值。 如果片上电压大于参考电压和由数字偏移值识别的偏移的总和，则时钟控制电路抑制时钟脉冲的传输，以减少功耗。 可以数字调整偏移量以改变片内电压的平均电平。 在时钟控制的比较器中可以使用类似的数字调谐机构来将第一电压与数字可调阈值电压进行比较。

    Controlling Voltage Generation and Voltage Comparison
    5.
    发明申请
    Controlling Voltage Generation and Voltage Comparison 有权
    控制电压产生和电压比较

    公开(公告)号：US20160118882A1

    公开(公告)日：2016-04-28

    申请号：US14922783

    申请日：2015-10-26

    Applicant: ARM Limited

    Inventor： Parameshwarappa Anand Kumar SAVANTH ,  James Edward MYERS ,  David Walter FLYNN ,  Bal S. SANDHU

    IPC: H02M3/157 ,  G01R19/00

    CPC classification number: H02M3/157 ,  G01R19/0084 ,  H02M3/07 ,  Y02B70/16

    Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

    Abstract translation: 集成电路具有用于响应于时钟脉冲从电源电压产生片上电压的电压产生电路。 时钟控制电路控制时钟脉冲的传输到电压产生电路。 时钟控制电路接收参考电压和包括识别偏移的二进制数值的数字偏移值。 如果片上电压大于参考电压和由数字偏移值识别的偏移的总和，则时钟控制电路抑制时钟脉冲的传输，以减少功耗。 可以数字调整偏移量以改变片内电压的平均电平。 在时钟控制的比较器中可以使用类似的数字调谐机构来将第一电压与数字可调阈值电压进行比较。

    DATA TRANSFER BETWEEN USER-WORN DEVICES
    6.
    发明公开
    DATA TRANSFER BETWEEN USER-WORN DEVICES 审中-公开

    公开(公告)号：US20230367394A1

    公开(公告)日：2023-11-16

    申请号：US18313102

    申请日：2023-05-05

    Applicant: Arm Limited

    Inventor： Emre OZER ,  Parameshwarappa Anand Kumar SAVANTH ,  Jedrzej KUFEL ,  Sahan Sajeewa Hiniduma Udugama GAMAGE ,  John Philip BIGGS

    IPC: G06F3/01 ,  A61B5/256 ,  A61B5/00

    CPC classification number: G06F3/015 ,  A61B5/256 ,  A61B5/7285

    Abstract: Wearable devices, systems of wearable devices, and methods of operating the same are disclosed. A first wearable device worn in contact with the user’s skin monitors the user and comprises a transmission electrode in contact with the user’s skin. A second wearable device comprises a reception electrode worn in contact with the user’s skin. The first wearable device can apply an alert signal to the transmission electrode and measures a transmission current at the transmission electrode. The second wearable device monitors an electrical status of the reception electrode and when the alert signal is detected applies an alert response signal to the receiver electrode. The first wearable device identifies application of the alert response signal to the receiver electrode by measurement of a variation of the transmission current at the transmission electrode whilst the alert signal is applied to the transmission electrode.

    SMART LABELS
    7.
    发明申请
    SMART LABELS 有权

    公开(公告)号：US20220230033A1

    公开(公告)日：2022-07-21

    申请号：US17595880

    申请日：2020-03-12

    Applicant: Arm Limited

    Inventor： Emre ÖZER ,  Parameshwarappa Anand Kumar SAVANTH ,  Jedrzej KUFEL

    IPC: G06K19/07 ,  H02J50/00 ,  G06K7/00 ,  G06K7/10 ,  G09F3/02

    Abstract: Smart labels, methods of operating smart labels, and associated contexts in which such smart labels may be used are disclosed. The smart label, for use in conjunction with consumer product packaging, comprises an energy harvester to capture ambient energy to provide a source of electrical energy and electronic circuitry powered by the electrical energy. A fuse provides an electrical connection between the energy harvester and the electronic circuitry and destruction of the fuse permanently disconnects the energy harvester from the electronic circuitry. Unnecessary continued operation of the electronic circuitry powered by the energy harvester can therefore be prevented, for example when the consumer product packaging is disposed of or recycled, which may be an undesirable heat source. Smart labelling, and a connected network of smart bins which can read the smart labelling, may also be used to promote consumer recycling of consumer product packaging.

    CHECKPOINTING
    8.
    发明公开
    CHECKPOINTING 审中-公开

    公开(公告)号：US20230376218A1

    公开(公告)日：2023-11-23

    申请号：US18316538

    申请日：2023-05-12

    Applicant: Arm Limited

    Inventor： Fernando GARCIA REDONDO ,  Sahan Sajeewa Hiniduma Udugama GAMAGE ,  Jonas ŠVEDAS ,  Parameshwarappa Anand Kumar SAVANTH

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673

    Abstract: In response to a power-loss warning event occurring during data processing, a checkpointing process is performed to save a checkpoint of context data associated with the data processing to non-volatile data storage. In response to detection of a power recovery event occurring when the checkpointing process is still in progress, it is determined whether a checkpoint abort condition is satisfied, based at least on a checkpoint progress indication indicative of progress of the checkpointing process. If the checkpoint abort condition is unsatisfied, the checkpointing process can continue. If the checkpoint abort condition is satisfied, the checkpointing process is aborted to allow the data processing to resume.

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