公开(公告)号：US20160118882A1

公开(公告)日：2016-04-28

申请号：US14922783

申请日：2015-10-26

Applicant: ARM Limited

Inventor： Parameshwarappa Anand Kumar SAVANTH ,  James Edward MYERS ,  David Walter FLYNN ,  Bal S. SANDHU

IPC: H02M3/157 ,  G01R19/00

CPC classification number: H02M3/157 ,  G01R19/0084 ,  H02M3/07 ,  Y02B70/16

Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract translation: 集成电路具有用于响应于时钟脉冲从电源电压产生片上电压的电压产生电路。 时钟控制电路控制时钟脉冲的传输到电压产生电路。 时钟控制电路接收参考电压和包括识别偏移的二进制数值的数字偏移值。 如果片上电压大于参考电压和由数字偏移值识别的偏移的总和，则时钟控制电路抑制时钟脉冲的传输，以减少功耗。 可以数字调整偏移量以改变片内电压的平均电平。 在时钟控制的比较器中可以使用类似的数字调谐机构来将第一电压与数字可调阈值电压进行比较。

公开(公告)号：US20180217648A1

公开(公告)日：2018-08-02

申请号：US15419293

申请日：2017-01-30

Applicant: ARM Limited

Inventor： David Walter FLYNN ,  Vasan VENKATARAMAN

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/266 ,  G06F1/3287 ,  G06F1/3296 ,  H04W52/0209 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/162

Abstract: A system comprises a first domain 4 and second domain 6 which communicate via an interface 8. The first domain 4 transmits power state commands to the second domain 6 for controlling transitions of power states at the second domain 6. The power state commands include at least a power up command 50 for triggering a transition to a power up state and a power no-operation command 52 in response to which the second domain remains in the current one of the power states. The no-operation command 52 enables the second domain 6 to be left in either the power up state or a different power state even if the first domain 4 is powered down.

公开(公告)号：US20180032455A1

公开(公告)日：2018-02-01

申请号：US15219466

申请日：2016-07-26

Applicant: ARM LIMITED

Inventor： Parameshwarappa Anand Kumar SAVANTH ,  James Edward MYERS ,  David Walter FLYNN ,  Rohan GADDH ,  Rohit GROVER

IPC: G06F13/28 ,  G11C11/406 ,  G06F13/24

CPC classification number: G06F13/28 ,  G06F1/3287 ,  G06F9/4418 ,  G06F13/24 ,  G11C11/40615

Abstract: An interface device for a data processing system is provided. The interface device comprises first interface circuitry to receive incoming data and second interface circuitry to transmit processed data to a data store for storage. The interface device is provided with processing circuitry to generate the processed data from the incoming data wherein the processing carried out reduces the data in size. The processing circuitry is also responsive to at least one characteristic of the incoming data or the processed data to transmit a notification signal to a data processing component of the data processing system.

公开(公告)号：US20140340122A1

公开(公告)日：2014-11-20

申请号：US13895624

申请日：2013-05-16

Applicant: ARM LIMITED

Inventor： Parameshwarappa Anand Kumar SAVANTH ,  James Edward MYERS ,  David Walter FLYNN ,  Bal S. SANDHU

IPC: H02M3/156 ,  G01R19/00

CPC classification number: H02M3/157 ,  G01R19/0084 ,  H02M3/07 ,  Y02B70/16

Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract translation: 集成电路具有用于响应于时钟脉冲从电源电压产生片上电压的电压产生电路。 时钟控制电路控制时钟脉冲的传输到电压产生电路。 时钟控制电路接收参考电压和包括识别偏移的二进制数值的数字偏移值。 如果片上电压大于参考电压和由数字偏移值识别的偏移的总和，则时钟控制电路抑制时钟脉冲的传输，以减少功耗。 可以数字调整偏移量以改变片内电压的平均电平。 在时钟控制的比较器中可以使用类似的数字调谐机构来将第一电压与数字可调阈值电压进行比较。

公开(公告)号：US20190164582A1

公开(公告)日：2019-05-30

申请号：US15764437

申请日：2016-11-30

Applicant: ARM LIMITED

Inventor： James Edward MYERS ,  David Walter FLYNN

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/419 ,  G11C16/30

Abstract: A data buffer comprises data storage circuitry; input circuitry to input data to be stored by the data storage circuitry at a first operating voltage; output circuitry to output stored data from the data storage circuitry at a second operating voltage different to the first operating voltage; and control circuitry to control an operating voltage of the data storage circuitry to be substantially the first operating voltage during a data input operation by the input circuitry and to be substantially the second operating voltage during a data output operation by the output circuitry.

公开(公告)号：US20170201099A1

公开(公告)日：2017-07-13

申请号：US15313599

申请日：2015-05-11

Applicant: ARM Limited

Inventor： Parameshwarappa Anand Kumar SAVANTH ,  James Edward MYERS ,  David Walter FLYNN

IPC: H02J3/38 ,  G05B15/02 ,  H02M3/04

CPC classification number: H02J50/00 ,  G05B15/02 ,  H02J3/383 ,  H02J7/025 ,  H02J17/00 ,  H02J50/40 ,  H02M3/04

Abstract: An electronic device 50 has at least one harvesting unit 52 for harvesting power from ambient energy. At least one circuit 54, including processing circuitry 56, is supplied with power from the harvesting unit 52. Control circuitry 60 is provided to adjust at least one property of the processing circuitry 56 or the at least one harvesting unit 52 to reduce impedance mismatch between an output impedance of the harvesting unit 52 and an input impedance of the at least one circuit 54.

公开(公告)号：US20160170465A1

公开(公告)日：2016-06-16

申请号：US14907945

申请日：2014-06-16

Applicant: ARM LIMITED

Inventor： David Walter FLYNN ,  James Edward MYERS

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/3024 ,  G06F11/3058 ,  G06F11/3096 ,  G06F13/00 ,  Y02D10/126 ,  Y02D10/172

Abstract: Mechanisms are provided for energy management signalling with an apparatus for processing data, such as a system-on-chip integrated circuit (2). Processing circuitry (6, 8, 10) is coupled to consumer energy interface circuitry (14, 16, 18) which communicates with energy management circuitry (4). The energy management signals which are communicated include a static power consumption signal indicative of a level of power consumption which is independent of processing operations being performed and a dynamic power consumption signal indicative of a level of dynamic power consumption which is dependent upon the processing operations being performed.

Abstract translation: 提供了用于处理数据的装置的能量管理信令的机制，例如片上系统集成电路（2）。 处理电路（6,8,10）耦合到与能量管理电路（4）通信的消费者能量接口电路（14,16,18）。 所传送的能量管理信号包括指示与所执行的处理操作无关的功率消耗水平的静态功耗信号，以及指示取决于处理操作的动态功耗水平的动态功耗信号 执行。

公开(公告)号：US20160374029A1

公开(公告)日：2016-12-22

申请号：US15166315

申请日：2016-05-27

Applicant: ARM LIMITED

Inventor： David Walter FLYNN

IPC: H04W52/22 ,  H04L12/26 ,  H04L12/873 ,  H04L5/00

CPC classification number: H04W52/221 ,  G06F13/42 ,  G06F13/4269 ,  H04L47/13

Abstract: A data transfer system, a method of data transfer and a corresponding transmitter and receiver are disclosed. A communication protocol between the transmitter and receiver is defined using a set of valid transmission states for communication from the transmitter to the receiver and a set of valid acknowledgement states for transmission from the receiver to the transmitter. A Hamming distance between patterns of zeroes, and between patterns of ones, in valid states of each of these sets is at least one and the transmitter is arranged to transition between a number of transmission states in response to the reception of an acknowledgement state from the receiver which matches a transmission state it has sent to the receiver on a request bus. A communication protocol which is robust across a multi-voltage and/or clock domain interface is thus provided.

Abstract translation: 公开了一种数据传输系统，数据传输方法和相应的发射机和接收机。 使用用于从发射机到接收机的通信的一组有效传输状态和用于从接收机到发射机的传输的一组有效的确认状态来定义发射机和接收机之间的通信协议。 在这些集合中的每一个的有效状态下，零模式和模式之间的汉明距离是至少一个，并且发射机被布置为响应于来自所述发射机的接收到确认状态而在多个发射状态之间转换 接收机，其匹配其在请求总线上发送到接收器的传输状态。 因此提供了在多电压和/或时钟域接口上稳健的通信协议。

公开(公告)号：US20150054563A1

公开(公告)日：2015-02-26

申请号：US14327004

申请日：2014-07-09

Applicant: ARM Limited

Inventor： David Walter FLYNN ,  James Edward MYERS

IPC: H03K3/012

CPC classification number: H03K19/017509

Abstract: An integrated circuit 6 including a first voltage domain 4 incorporates real time clock circuitry 12 that communicates via communication circuitry 18 with processing circuitry 16 contained within a second voltage domain. The communication circuitry 18 includes first parallel-to-serial conversion circuitry 24 located within the first voltage domain 4, level shifting circuitry 32 for passing serial signals between the voltage domains and second parallel-to-serial circuitry 26 located in the second voltage domain.

Abstract translation: 包括第一电压域4的集成电路6包括经由通信电路18与包含在第二电压域内的处理电路16进行通信的实时时钟电路12。 通信电路18包括位于第一电压域4内的第一并行到串行转换电路24，用于在电压域之间传递串行信号的电平移位电路32和位于第二电压域中的第二并行 - 串行电路26。