公开(公告)号：US20230178819A1

公开(公告)日：2023-06-08

申请号：US17541000

申请日：2021-12-02

Applicant: Arm Limited

Inventor： Emre OZER ,  Remy POTTIER ,  Jedrzej KUFEL ,  John Philip BIGGS ,  James Edward MYERS

IPC: H01M10/48 ,  G01R31/392

CPC classification number: H01M10/482 ,  G01R31/392

Abstract: A battery cell monitoring system comprises a flexible substrate able to conform to a surface of a battery cell to be monitored, and a plurality of first-level prediction units integrated onto the flexible substrate, where each first-level prediction unit is positioned at a different location on the flexible substrate to each other first-level prediction unit. Each first-level prediction unit comprises at least one sensor to generate sensor signals indicative of a physical state of the battery cell, and first-level prediction circuitry to generate a predicted battery cell status value in dependence on the sensor signals received from the at least one sensor of that first-level prediction unit. Second-level prediction circuitry is arranged to determine a prediction result in dependence on the predicted battery cell status values generated by the first-level prediction circuitry of each first-level prediction unit, and a communications device is used to output the prediction result at least when the prediction result indicates an occurrence of a critical event.

公开(公告)号：US20230051410A1

公开(公告)日：2023-02-16

申请号：US17398198

申请日：2021-08-10

Applicant: Arm Limited

Inventor： James Edward MYERS ,  Emre ÖZER ,  Remy POTTIER ,  Jedrzej KUFEL ,  John Philip BIGGS

IPC: G08B21/18 ,  G08B5/36

Abstract: Apparatus comprises at least one visual indicator element; at least one detector to detect access to the apparatus consistent with a cleaning operation being applied to a surface of the apparatus; and processing circuitry to control a visual indication state of the at least one visual indicator element in response to a detection by the detector of access to the surface of the apparatus.

公开(公告)号：US20180032455A1

公开(公告)日：2018-02-01

申请号：US15219466

申请日：2016-07-26

Applicant: ARM LIMITED

Inventor： Parameshwarappa Anand Kumar SAVANTH ,  James Edward MYERS ,  David Walter FLYNN ,  Rohan GADDH ,  Rohit GROVER

IPC: G06F13/28 ,  G11C11/406 ,  G06F13/24

CPC classification number: G06F13/28 ,  G06F1/3287 ,  G06F9/4418 ,  G06F13/24 ,  G11C11/40615

Abstract: An interface device for a data processing system is provided. The interface device comprises first interface circuitry to receive incoming data and second interface circuitry to transmit processed data to a data store for storage. The interface device is provided with processing circuitry to generate the processed data from the incoming data wherein the processing carried out reduces the data in size. The processing circuitry is also responsive to at least one characteristic of the incoming data or the processed data to transmit a notification signal to a data processing component of the data processing system.

公开(公告)号：US20140340122A1

公开(公告)日：2014-11-20

申请号：US13895624

申请日：2013-05-16

Applicant: ARM LIMITED

Inventor： Parameshwarappa Anand Kumar SAVANTH ,  James Edward MYERS ,  David Walter FLYNN ,  Bal S. SANDHU

IPC: H02M3/156 ,  G01R19/00

CPC classification number: H02M3/157 ,  G01R19/0084 ,  H02M3/07 ,  Y02B70/16

Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract translation: 集成电路具有用于响应于时钟脉冲从电源电压产生片上电压的电压产生电路。 时钟控制电路控制时钟脉冲的传输到电压产生电路。 时钟控制电路接收参考电压和包括识别偏移的二进制数值的数字偏移值。 如果片上电压大于参考电压和由数字偏移值识别的偏移的总和，则时钟控制电路抑制时钟脉冲的传输，以减少功耗。 可以数字调整偏移量以改变片内电压的平均电平。 在时钟控制的比较器中可以使用类似的数字调谐机构来将第一电压与数字可调阈值电压进行比较。

公开(公告)号：US20230031751A1

公开(公告)日：2023-02-02

申请号：US17390436

申请日：2021-07-30

Applicant: Arm Limited

Inventor： Emre ÖZER ,  James Edward MYERS ,  Jedrzej KUFEL ,  John Philip BIGGS ,  Remy POTTIER

IPC: G07C13/02 ,  G06K19/077 ,  G06K19/02 ,  G06K7/08 ,  G06Q90/00 ,  H05K1/16 ,  H05K1/03 ,  H05K3/12

Abstract: Aspects of the present disclosure relate to an apparatus comprising: a substrate; communication circuitry deposited on said substrate; and ballot circuitry deposited on said substrate. The ballot circuitry comprises: a plurality of voting circuitry elements, each voting circuitry element being responsive to a voting operation to change a conductive state of that voting circuitry element; and logic circuitry communicatively coupled with each of the plurality of voting circuitry elements and with the communication circuitry. The logic circuitry is configured to: detect the conductive state of each of the plurality of voting circuitry elements; and transmit, via the communication circuitry and based on the conductive state of each of the plurality of voting circuitry elements, a voting result.

公开(公告)号：US20160321389A1

公开(公告)日：2016-11-03

申请号：US14697709

申请日：2015-04-28

Applicant: ARM LIMITED

Inventor： James Edward MYERS

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/092

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  H01L27/0207 ,  H01L27/092

Abstract: A computer implemented method and a computer program for generating a layout of a circuit block of an integrated circuit are provided. Input data is received identifying a plurality of circuit elements and interconnections required to implement the circuit block, and the method also has access to a cell library providing a plurality of standard cells, where each standard cell defines a corresponding circuit element using transistors, the transistors comprising n-type transistors and p-type transistors. A plurality of rows are formed within which to place standard cells from the cell library in order to implement the circuit block, the plurality of rows including at least one body biased row in which a body bias is to be applied in respect of either the n-type transistors or the p-type transistors provided by the standard cells placed in that body biased row. Constraint data is specified identifying a subset of the standard cells that are allowed to be placed in each body biased row, and the layout is then generated by placing standard cells within the plurality of rows having regard to the input data, an indication of each body biased row, and the constraint data for each body biased row. This enables a significant improvement in the benefits that can be achieved through the use of body biasing mechanisms, for example allowing a significant increase in switching speed of the circuit block to be achieved, without a significant increase in leakage current.

Abstract translation: 提供了一种用于产生集成电路的电路块的布局的计算机实现的方法和计算机程序。 接收输入数据，识别实现电路块所需的多个电路元件和互连，并且该方法还可以访问提供多个标准单元的单元库，其中每个标准单元使用晶体管定义相应的电路元件，晶体管 包括n型晶体管和p型晶体管。 形成多个行以在其中放置来自单元库的标准单元以实现电路块，所述多行包括至少一个主体偏置行，其中相对于n 型晶体管或由放置在该主体偏置行中的标准单元提供的p型晶体管。 指定约束数据，识别允许放置在每个正偏置行中的标准单元的子集，然后通过在考虑到输入数据的多行中放置标准单元来生成布局，每个主体的指示 偏置行，以及每个主体偏置行的约束数据。 这使得能够通过使用主体偏置机构可以实现的益处得到显着改善，例如允许实现电路块的开关速度的显着增加，而不会显着增加泄漏电流。

公开(公告)号：US20150054563A1

公开(公告)日：2015-02-26

申请号：US14327004

申请日：2014-07-09

Applicant: ARM Limited

Inventor： David Walter FLYNN ,  James Edward MYERS

IPC: H03K3/012

CPC classification number: H03K19/017509

Abstract: An integrated circuit 6 including a first voltage domain 4 incorporates real time clock circuitry 12 that communicates via communication circuitry 18 with processing circuitry 16 contained within a second voltage domain. The communication circuitry 18 includes first parallel-to-serial conversion circuitry 24 located within the first voltage domain 4, level shifting circuitry 32 for passing serial signals between the voltage domains and second parallel-to-serial circuitry 26 located in the second voltage domain.

Abstract translation: 包括第一电压域4的集成电路6包括经由通信电路18与包含在第二电压域内的处理电路16进行通信的实时时钟电路12。 通信电路18包括位于第一电压域4内的第一并行到串行转换电路24，用于在电压域之间传递串行信号的电平移位电路32和位于第二电压域中的第二并行 - 串行电路26。

公开(公告)号：US20230117908A1

公开(公告)日：2023-04-20

申请号：US17501836

申请日：2021-10-14

Applicant: Arm Limited

Inventor： Remy POTTIER ,  Emre ÖZER ,  John Philip BIGGS ,  James Edward MYERS ,  Jedrzej KUFEL

IPC: H02J7/00 ,  G01R31/382 ,  H01M10/48 ,  G06N20/00

Abstract: Battery cell monitoring systems comprising a flexible substrate and components integrated onto the flexible substrate, and methods of operating the same are disclosed. The components comprise a computing device and at least one sensor, where the at least one sensor is configured to generate sensor signals indicative of a physical state of the battery cell. The computing device is configured to hold characteristic data values which have been generated based on prior sensor signals. The computing device is configured to receive the sensor signals from the at least one sensor and to generate battery cell status data in dependence on the sensor signals and the characteristic data values.

公开(公告)号：US20230048259A1

公开(公告)日：2023-02-16

申请号：US17817686

申请日：2022-08-05

Applicant: Arm Limited

Inventor： James Edward MYERS ,  Shidhartha DAS

IPC: G06F12/14 ,  G06F21/72

Abstract: An integrated circuit device including processing circuitry, communications circuitry configured to provide a communication link with a communication apparatus external to the integrated circuit device, and a memory accessible by the processing circuitry and by the communications circuitry, the memory comprising a memory region to which the processing circuitry has write access and to which the communications circuitry has read access, in which the processing circuitry is configured to write information to the memory region indicative of one or more use conditions of the integrated circuit device, and in which the communications circuitry is configured to access the memory region and to provide the information indicative of the one or more use conditions of the integrated circuit device via the communication link.

公开(公告)号：US20190164582A1

公开(公告)日：2019-05-30

申请号：US15764437

申请日：2016-11-30

Applicant: ARM LIMITED

Inventor： James Edward MYERS ,  David Walter FLYNN

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/419 ,  G11C16/30

Abstract: A data buffer comprises data storage circuitry; input circuitry to input data to be stored by the data storage circuitry at a first operating voltage; output circuitry to output stored data from the data storage circuitry at a second operating voltage different to the first operating voltage; and control circuitry to control an operating voltage of the data storage circuitry to be substantially the first operating voltage during a data input operation by the input circuitry and to be substantially the second operating voltage during a data output operation by the output circuitry.