公开(公告)号：US20140289501A1

公开(公告)日：2014-09-25

申请号：US13847892

申请日：2013-03-20

Applicant: ARM Limited

Inventor： Guillaume SCHON ,  Cedric Denis Robert AIRAUD ,  Frederic Jean Denis ARSANTO ,  Luca SCALABRINO

IPC: G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30098 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3863

Abstract: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.

Abstract translation: 用于处理装置的注册重命名电路，被配置为处理来自指定集合的​​指令集的指令流，所述指令集指定来自架构的一组寄存器。 该装置包括被配置为存储由处理装置处理的数据值的寄存器的物理组。 寄存器重命名电路被配置为从指令解码器接收操作流，并将要由操作流写入的寄存器映射到当前可用的寄存器的物理组内的物理寄存器。 寄存器重命名电路包括寄存器释放电路，其被配置为当满足第一组条件时释放已经被映射到寄存器的物理寄存器，并且当第二组存储器被释放时已被映射到附加寄存器的物理寄存器 条件得到满足。

公开(公告)号：US20140215189A1

公开(公告)日：2014-07-31

申请号：US13752621

申请日：2013-01-29

Applicant: ARM LIMITED

Inventor： Cedric Denis Robert AIRAUD ,  Luca SCALABRINO ,  Frederic Jean Denis ARSANTO ,  Guillaume SCHON ,  Frederic Claude Marie PIRY ,  Albin Pierick TONNERRE

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30014 ,  G06F9/30196

Abstract: An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.

Abstract translation: 一种装置和方法包括执行电路，其包括宽操作数执行单元，其被配置为允许在单个指令的执行期间处理最多N位的操作数数据。 解码器电路针对每个指令对至少一个控制数据块进行解码并生成至少一个控制数据块，该控制数据块标识由执行电路执行的操作和用于该指令的至少两个可重新组合的控制数据块。 发出队列控制电路然后为发送队列中的每个至少两个数据块和相关操作数数据的高达M位分配一个时隙，并标记这些分配的时隙以标识它们包含可重新组合的控制数据块。 所述问题队列控制电路与包含在所述至少两个控制数据块的所分配的时隙中的操作数数据一起向所述宽操作数执行单元发出组合块。

公开(公告)号：US20160335088A1

公开(公告)日：2016-11-17

申请号：US15082601

申请日：2016-03-28

Applicant: ARM LIMITED

Inventor： Luca SCALABRINO ,  Frederic Jean Denis ARSANTO ,  Thomas Gilles TARRIDEC ,  Cedric Denis Robert AIRAUD

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/3857

Abstract: A data processing apparatus comprises register rename circuitry for mapping architectural register specifiers specified by instructions to physical registers to be accessed in response to the instructions. Available register control circuitry controls which physical registers are available for mapping to an architectural register specifier by the register rename circuitry. For at least one group of two or more physical registers, the available register control circuitry controls availability of the registers based on a group tracking indication indicative of whether there is at least one pending access to any of the physical registers in the group.

Abstract translation: 数据处理装置包括寄存器重命名电路，用于将由指令指定的体系结构寄存器指定符映射到要响应于指令进行访问的物理寄存器。 可用的寄存器控制电路控制哪些物理寄存器可用于通过寄存器重命名电路映射到架构寄存器说明符。 对于至少一组两个或更多个物理寄存器，可用的寄存器控制电路基于组跟踪指示来控制寄存器的可用性，所述组跟踪指示指示是否存在至少一个待访问组中的任何物理寄存器。

公开(公告)号：US20140195787A1

公开(公告)日：2014-07-10

申请号：US13737153

申请日：2013-01-09

Applicant: ARM LIMITED

Inventor： Luca SCALABRINO ,  Melanie Emanuelle Lucie TEYSSIER ,  Cedric Denis Robert AIRAUD ,  Guillaume SCHON

IPC: G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885

Abstract: First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations.

Abstract translation: 第一处理电路处理程序指令流的至少一部分。 第一处理电路具有用于存储数据和寄存器重命名电路的寄存器，用于将架构寄存器说明符映射到物理寄存器说明符。 重命名数据存储存储用于识别架构和物理寄存器说明符之间的寄存器映射的重命名条目。 至少一些重命名条目具有指示在生成先前计数值和生成计数值之间发生的推测点数的计数值。 推测点可以例如是分支操作或加载/存储操作。

公开(公告)号：US20240028516A1

公开(公告)日：2024-01-25

申请号：US18147068

申请日：2022-12-28

Applicant: Arm Limited

Inventor： Luca MARONCELLI ,  Cedric Denis Robert AIRAUD ,  Florent BEGON ,  Peter Raphael EID

IPC: G06F12/0862 ,  G06F12/0875

CPC classification number: G06F12/0862 ,  G06F12/0875 ,  G06F2212/6022

Abstract: A data processing apparatus is provided. Prefetch circuitry generates a prefetch request for a cache line prior to the cache line being explicitly requested. The cache line is predicted to be required for a store operation in the future. Issuing circuitry issues the prefetch request to a memory hierarchy and filter circuitry filters the prefetch request based on at least one other prefetch request made to the cache line, to control whether the prefetch request is issued by the issuing circuitry.

公开(公告)号：US20230289185A1

公开(公告)日：2023-09-14

申请号：US18178123

申请日：2023-03-03

Applicant: Arm Limited

Inventor： Michael Jean SOLE ,  Cedric Denis Robert AIRAUD

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3836

Abstract: A data processing apparatus comprises processing circuitry to execute processing instructions, the processing circuitry comprising: a set of physical registers; instruction decoder circuitry to decode processing instructions; detector circuitry to detect groups of instructions which comply with a conflict condition, in which a group of instructions complies with the conflict condition at least when a given storage element is written to by a maximum of one instruction of that group of instructions; instruction issue circuitry to issue decoded instructions for execution; and instruction execution circuitry to execute instructions decoded by the instruction decoder circuitry.

公开(公告)号：US20200073660A1

公开(公告)日：2020-03-05

申请号：US16118528

申请日：2018-08-31

Applicant: Arm Limited

Inventor： Xiaoyang SHEN ,  Cedric Denis Robert AIRAUD ,  Luca NASSI ,  Damien Robin MARTIN

IPC: G06F9/30 ,  G06F5/01

Abstract: Apparatus comprises counter and bit-shift circuitry to provide a succession of processing stages each comprising a count operation stage and a corresponding bit-shift stage, each processing stage operating with respect to a set of contiguous n-bit groups of bit positions, where n is 1 for a first processing stage and n doubles from one processing stage in the succession of processing stages to a next processing stage in the succession of processing stages; each count operation stage being configured to generate, for a first set of alternate instances of the n-bit groups of bit positions, count values indicating a respective number of bits of a predetermined bit value in a mask data word; and each bit-shift stage being configured to generate a bit-shifted data word by bit-shifting bits of a data word to be processed, for a second set of alternate instances of the n-bit groups of bit positions complementary to the first set, by respective numbers of bit positions dependent upon the count values generated by the respective count operation stage, in which the bit-shifted data word for one bit-shift stage in the succession of processing stages is used as the data word to be processed by the next bit-shift stage in the succession of processing stages.

公开(公告)号：US20190377706A1

公开(公告)日：2019-12-12

申请号：US16005790

申请日：2018-06-12

Applicant: Arm Limited

Inventor： Cedric Denis Robert AIRAUD ,  Luca NASSI ,  Damien Robin MARTIN ,  Xiaoyang SHEN

IPC: G06F15/80 ,  G06F9/38 ,  G06F9/30 ,  G06F1/32

Abstract: Apparatuses and methods of data processing are disclosed. An apparatus comprises two data processing clusters each having multiple data processing lanes to perform single instruction multiple data (SIMD) processing. Decoded instructions are issued to at least one of the two data processing clusters. A decoded SIMD instruction specifying a vector length which is more than the width of the data processing lanes of the first data processing cluster has a first part issued to the first data processing cluster for execution. An issuance target for a second remaining part of the decoded SIMD instruction is selected in dependence on a dynamic performance condition. When the dynamic performance condition has a first state the issuance target is the first data processing cluster and when the dynamic performance condition has a second state the issuance target is the second data processing cluster. When the issuance target is the first data processing cluster, to schedule the first and second parts of the decoded SIMD instruction in series.

公开(公告)号：US20160335085A1

公开(公告)日：2016-11-17

申请号：US15076889

申请日：2016-03-22

Applicant: ARM LIMITED

Inventor： Luca SCALABRINO ,  Frederic Jean Denis ARSANTO ,  Thomas Gilles TARRIDEC ,  Cedric Denis Robert AIRAUD

IPC: G06F9/30

CPC classification number: G06F9/30087 ,  G06F8/458 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3877 ,  G06F9/522

Abstract: A data processing system 2 includes multiple out-of-order issue queues 8, 10. A master serialisation instruction MSI received by a first issue queue 8 is detected by slave generation circuitry 24 which generates a slave serialisation instruction SSI added to a second issue queue 10. The master serialisation instruction MSI manages serialisation relative to the instructions within the first issue queue 8. The slave serialisation instruction SSI manages serialisation relative to the instructions within the second issue queue 10. The master serialisation instruction MSI and the slave serialisation instruction SSI are removed when both have met their serialisation conditions and are respectively the oldest instructions within their issue queues.

Abstract translation: 数据处理系统2包括多个无序发行队列8,10。由第一发行队列8接收的主序列化指令MSI由从属产生电路24检测，该生成电路产生附加到第二发行队列的从串行化指令SSI 主序列化指令MSI管理相对于第一个问题队列8内的指令的串行化。从串行化指令SSI管理相对于第二个发布队列10内的指令的串行化。主序列化指令MSI和从串行化指令SSI是 当两者都满足其序列化条件并分别是其问题队列中的最早的指令时被移除。

公开(公告)号：US20140195780A1

公开(公告)日：2014-07-10

申请号：US13737137

申请日：2013-01-09

Applicant: ARM LIMITED

Inventor： Nicolas CHAUSSADE ,  Luca SCALABRINO ,  Frederic Jean Denis ARSANTO ,  Cedric Denis Robert AIRAUD

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30072 ,  G06F9/3826

Abstract: A data processing apparatus comprises first and second processing circuitry. A conditional instruction executed by the second processing circuitry may have an outcome which is dependent on one of a plurality of sets of condition information maintained by the first processing circuitry. A first forwarding path can forward the sets of condition information from the first processing circuitry to a predetermined pipeline stage of a processing pipeline of the second processing circuitry. A request path can transmit a request signal from the second processing circuitry to the first processing circuitry, the request signal indicating a requested set of condition information which was not yet valid when a conditional instruction was at the predetermined pipeline stage. A second forwarding path may forward the requested set of condition information to a subsequent pipeline stage when the information becomes valid.

Abstract translation: 数据处理装置包括第一和第二处理电路。 由第二处理电路执行的条件指令可以具有取决于由第一处理电路维护的多组条件信息之一的结果。 第一转发路径可将来自第一处理电路的条件信息集合转发到第二处理电路的处理流水线的预定流水线级。 请求路径可以将来自第二处理电路的请求信号发送到第一处理电路，该请求信号指示当条件指令处于预定流水线阶段时尚未有效的请求的条件信息集合。 当信息变得有效时，第二转发路径可以将所请求的条件信息集合转发到后续流水线级。