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公开(公告)号：US11455268B2
公开(公告)日：2022-09-27
申请号：US16790112
申请日：2020-02-13
Applicant: Arm Limited
Inventor： Matteo Maria Andreozzi , Michael Andrew Campbell , Giovanni Stea , Raffaele Zippo
Abstract: The present disclosure relates generally to electronic interconnects including one or more switches and, more particularly, to delay bound determination for electronic interconnects.
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公开(公告)号：US10509743B2
公开(公告)日：2019-12-17
申请号：US15612072
申请日：2017-06-02
Applicant: ARM LIMITED
Inventor： Daren Croxford , Sharjeel Saeed , Quinn Carter , Michael Andrew Campbell
Abstract: A master device has a buffer for storing data transferred from, or to be transferred to, a memory system. Control circuitry issues from time to time a group of one or more transactions to request transfer of a block of data between the memory system and the buffer. Hardware or software mechanism can be provided to detect at least one memory load parameter indicating how heavily loaded the memory system is, and a group size of the block of data transferred per group can be varied based on the memory load parameter. By adapting the size of the block of data transferred per group based on memory system load, a better balance between energy efficiency and quality of service can be achieved.
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公开(公告)号：US12153805B2
公开(公告)日：2024-11-26
申请号：US17755507
申请日：2020-09-01
Applicant: ARM LIMITED
Inventor： Michael Andrew Campbell , Matteo Maria Andreozzi , Lorenzo Biagini , Giovanni Stea , Ankit Mehta
IPC: G06F3/06
Abstract: Examples of the present disclosure relate to an apparatus comprising interface circuitry to receive memory access commands directed to a memory device, each memory access command specifying a memory address to be accessed. The apparatus comprises scheduler circuitry to store a representation of a plurality of states accessible to the memory device and, based on the representation, determine an order for the received memory access commands. The apparatus comprises dispatch circuitry to receive the received memory access commands from the scheduler circuitry and issue the received memory access commands, in the determined order, to be performed by the memory device.
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公开(公告)号：US10817336B2
公开(公告)日：2020-10-27
申请号：US15194928
申请日：2016-06-28
Applicant: ARM LIMITED
IPC: G06F9/48
Abstract: There is provided an apparatus comprising scheduling circuitry, which selects a task as a selected task to be performed from a plurality of queued tasks, each having an associated priority, in dependence on the associated priority of each queued task. Escalating circuitry increases the associated priority of each of the plurality of queued tasks after a period of time. The plurality of queued tasks comprises a time-sensitive task having an associated deadline and in response to the associated deadline being reached, the scheduling circuitry selects the time-sensitive task as the selected task to be performed.
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5.发明授权公开(公告)号：US09454451B2
公开(公告)日：2016-09-27
申请号：US13764050
申请日：2013-02-11
Applicant: ARM LIMITED
Inventor： Michael Andrew Campbell
CPC classification number: G06F11/3037 , G06F11/106
Abstract: An apparatus and method are provided for opportunistically performing scrubbing operations on a memory device. The apparatus is used for accessing the memory device in response to access requests issued by at least one requesting device and comprises interface circuitry that is configured to access the memory device in response to the access requests. The apparatus also comprises activity monitoring circuitry which generates memory access activity data that results from memory access activity between the interface circuitry and the memory device. Scrubbing circuitry is also included and is configured to issue scrubbing access requests to perform the scrubbing operations, the scrubbing access requests being issued in response to the memory access activity data indicating a trigger condition. The above apparatus allows scrubbing access requests to be issued taking into account actual memory access activity between the interface circuitry and the memory device, thereby allowing the access requests to be issued opportunistically in such a way that the performance cost/system power consumption necessary to achieve a particular reliability can be reduced compared to known techniques.
Abstract translation: 提供了一种用于机会地对存储器件进行擦洗操作的装置和方法。 所述设备用于响应于由至少一个请求设备发出的访问请求来访问存储设备，并且包括被配置为响应于访问请求访问存储设备的接口电路。 该装置还包括活动监视电路，其生成由接口电路和存储设备之间的存储器访问活动产生的存储器访问活动数据。 还包括擦洗电路，并且被配置为发出擦洗访问请求以执行擦洗操作，响应于指示触发条件的存储器访问活动数据发出擦洗访问请求。 上述装置允许考虑接口电路和存储器件之间的实际存储器访问活动来擦除访问请求，从而允许机会地发出访问请求，使得实现所需的性能成本/系统功耗 与已知技术相比，可以降低特定的可靠性。
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Patent Agency Ranking
公开(公告)号：US12010242B2
公开(公告)日：2024-06-11
申请号：US16925723
申请日：2020-07-10
Applicant: Arm Limited
Inventor： Roberto Avanzi , Andreas Lars Sandberg , Michael Andrew Campbell , Matthias Lothar Boettcher , Prakash S. Ramrakhyani
CPC classification number: H04L9/3242 , G06F21/57 , G06F21/64 , H04W12/06 , G06F12/0875 , G06F12/1408 , G06F21/79
Abstract: To protect the integrity of data stored in a protected area of memory, data in the protected area of memory is retrieved in data blocks and an authentication code is associated with a memory granule contiguously comprising a first data block and a second data block. Calculation of the authentication code comprises a cryptographic calculation based on a first hash value determined from the first data block and a second hash value determined from the second data block. A hash value cache is provided to store hash values determined from data blocks retrieved from the protected area of the memory. When the first data block and its associated authentication code are retrieved from memory, a lookup for the second hash value in the hash value cache is performed, and a verification authentication code is calculated for the memory granule to which that data block belongs. The integrity of the first data block is contingent on the verification authentication code matching the retrieved authentication code.
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公开(公告)号：US10540281B2
公开(公告)日：2020-01-21
申请号：US15407681
申请日：2017-01-17
Applicant: ARM Limited
Inventor： Paul Stanley Hughes , Michael Andrew Campbell
IPC: G06F12/00 , G06F12/0804 , G06F12/121 , G06F12/127 , G06F12/122 , G06F12/123 , G06F12/0888
Abstract: A cache to provide data caching in response to data access requests from at least one system device, and a method operating such a cache, are provided. Allocation control circuitry of the cache is responsive to a cache miss to allocate an entry of the multiple entries in the data caching storage circuitry in dependence on a cache allocation policy. Quality-of-service monitoring circuitry is responsive to a quality-of-service indication to modify the cache allocation policy with respect to allocation of the entry for the requested data item. The behaviour of the cache, in particular regarding allocation and eviction, can therefore be modified in order to seek to maintain a desired quality-of-service for the system in which the cache is found.
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公开(公告)号：US08918700B2
公开(公告)日：2014-12-23
申请号：US13764003
申请日：2013-02-11
Applicant: ARM Limited
Inventor： Michael Andrew Campbell , Thomas Kelshaw Conway
CPC classification number: G06F11/1012 , G06F11/1048
Abstract: An apparatus includes encoding circuitry to generate code words for storage in a memory device. Decoding circuitry is responsive to a read transaction to decode one or more code words read from the memory device in order to generate read data for outputting in response to the read transaction. The decoding circuitry comprises error correction circuitry configured, for each read code word, to perform an error correction process to detect and correct errors in up to P symbols of the code word, where P is dependent on the number of ECC symbols in the code word. Error tracking circuitry determines error quantity indication data indicative of the errors detected by the error correction circuitry, and in response to the error quantity indication data indicating that an error threshold condition has been reached, the apparatus transitions from a normal mode of operation to a safety mode of operation.
Abstract translation: 一种装置包括编码电路以产生用于存储在存储器件中的代码字。 解码电路响应于读取事务来解码从存储器件读取的一个或多个代码字，以便产生用于响应于读取事务而输出的读取数据。 解码电路包括纠错电路，为每个读码字配置，执行纠错处理以检测和纠正代码字最多P个符号的错误，其中P取决于代码字中的ECC符号的数目 。 错误跟踪电路确定指示由纠错电路检测到的错误的错误量指示数据，并且响应于指示已经达到错误阈值条件的错误量指示数据，装置从正常操作模式转换到安全 操作模式。
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公开(公告)号：US11520626B2
公开(公告)日：2022-12-06
申请号：US17028422
申请日：2020-09-22
Applicant: Arm Limited
Inventor： Michael Andrew Campbell , Peter Owen Hawkins , David Joseph Hawkins
Abstract: A method and system for an enhanced weighted fair queuing technique for a resource are provided. A plurality of request streams is received at a requestor, each request stream including request messages from a process executing on the requestor. The request messages of each request stream are apportioned to an input queue associated with the request stream; each input queue has a weight. A virtual finish time is determined for each request message based, at least in part, on the weights of the input queues. A sequence of request messages is determined based, at least in part, on the virtual finish times of the request messages. The sequence of request messages is enqueued into an output queue. The sequence of request messages is sent to a resource, over a connection, which provides a service for each process.
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公开(公告)号：US20220091886A1
公开(公告)日：2022-03-24
申请号：US17028422
申请日：2020-09-22
Applicant: Arm Limited
Inventor： Michael Andrew Campbell , Peter Owen Hawkins , David Joseph Hawkins
Abstract: A method and system for an enhanced weighted fair queuing technique for a resource are provided. A plurality of request streams is received at a requestor, each request stream including request messages from a process executing on the requestor. The request messages of each request stream are apportioned to an input queue associated with the request stream; each input queue has a weight. A virtual finish time is determined for each request message based, at least in part, on the weights of the input queues. A sequence of request messages is determined based, at least in part, on the virtual finish times of the request messages. The sequence of request messages is enqueued into an output queue. The sequence of request messages is sent to a resource, over a connection, which provides a service for each process.
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