公开(公告)号：US10366734B2

公开(公告)日：2019-07-30

申请号：US15424418

申请日：2017-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander W. Schaefer ,  Ravi T. Jotwani ,  Samiul Haque Khan ,  David Hugh McIntyre ,  Stephen Victor Kosonocky ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/08 ,  G11C11/418 ,  G11C5/14 ,  G11C11/413 ,  G11C11/419

Abstract: A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.

公开(公告)号：US10049726B1

公开(公告)日：2018-08-14

申请号：US15424367

申请日：2017-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander W. Schaefer ,  David H. McIntyre

IPC: G11C7/00 ,  G11C11/419 ,  G11C11/418 ,  G11C7/12 ,  G11C7/02 ,  G11C8/08

Abstract: A dynamic NOR circuit includes a pre-charge transistor coupled between a first voltage supply node and a dynamic node to pre-charge the dynamic node. The dynamic NOR circuit includes a first keeper circuit having a first keeper transistor and a second keeper transistor serially coupled between the first voltage supply node and the dynamic node. The dynamic NOR circuit includes a first pull down circuit coupled between the dynamic node and ground. A first input signal is coupled to a gate of a first pull-down transistor in the first pull-down circuit and is also coupled to a gate of the first keeper transistor. A first keeper enable signal is coupled to a gate of the second keeper transistor. Additional keeper circuits and pull down circuits coupled to the dynamic node allow the dynamic NOR structure to handle a plurality of input signals.

公开(公告)号：US20180226111A1

公开(公告)日：2018-08-09

申请号：US15424418

申请日：2017-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander W. Schaefer ,  Ravi T. Jotwani ,  Samiul Haque Khan ,  David Hugh McIntyre ,  Stephen Victor Kosonocky ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/08 ,  G06F3/06

CPC classification number: G11C8/08 ,  G11C5/145 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419

Abstract: A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.

公开(公告)号：US20230334214A1

公开(公告)日：2023-10-19

申请号：US17722009

申请日：2022-04-15

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Alexander W. Schaefer ,  Robin Andrew Joyce ,  Shaun M. Kittle ,  Scott Eugene Swanstrom ,  Josef Alexander Czaban

IPC: G06F30/392 ,  G03F1/68

CPC classification number: G06F30/392 ,  G03F1/68 ,  G06F2119/18

Abstract: A system and method for creating layout for semiconductor chips are described. In various implementations, an integrated circuit includes at least a first functional block and a second functional block. The first functional block includes circuitry that has a first set of parameters of a first process corner. The second functional block includes circuitry that has a second set of parameters of a second process corner different from the first set of parameters of the first process corner. For a same set of operating conditions, the second functional block has device characteristics different from device characteristics of the first functional block based on the first process corner and the second process corner being different from one another. The integrated circuit is fabricated with a process corner mask that indicates which areas of the die use the first process corner and which areas use the second process corner.

公开(公告)号：US20180226968A1

公开(公告)日：2018-08-09

申请号：US15492249

申请日：2017-04-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander W. Schaefer

IPC: H03K19/00 ,  H03K19/20

CPC classification number: H03K19/0013 ,  H03K19/20

Abstract: A dynamic logic circuit includes a pull-up network coupled between a voltage supply and a dynamic node and receives a first input signal and a second input signal. A pull-down network is coupled between the dynamic node and a ground node and receives the first input signal and the second input signal. A pre-charge network is in parallel with the pull-up or pull-down network and pre-charges the dynamic node to a high or low voltage level prior to evaluation of the first and second input signals. The transistors in the pull-up network are substantially different in size than the transistors in the pull-down network.

公开(公告)号：US20180226122A1

公开(公告)日：2018-08-09

申请号：US15424367

申请日：2017-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander W. Schaefer ,  David H. McIntyre

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/02 ,  G11C7/12 ,  G11C8/08 ,  G11C11/418 ,  G11C2207/104

Abstract: A dynamic NOR circuit includes a pre-charge transistor coupled between a first voltage supply node and a dynamic node to pre-charge the dynamic node. The dynamic NOR circuit includes a first keeper circuit having a first keeper transistor and a second keeper transistor serially coupled between the first voltage supply node and the dynamic node. The dynamic NOR circuit includes a first pull down circuit coupled between the dynamic node and ground. A first input signal is coupled to a gate of a first pull-down transistor in the first pull-down circuit and is also coupled to a gate of the first keeper transistor. A first keeper enable signal is coupled to a gate of the second keeper transistor. Additional keeper circuits and pull down circuits coupled to the dynamic node allow the dynamic NOR structure to handle a plurality of input signals.