公开(公告)号：US10366734B2

公开(公告)日：2019-07-30

申请号：US15424418

申请日：2017-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander W. Schaefer ,  Ravi T. Jotwani ,  Samiul Haque Khan ,  David Hugh McIntyre ,  Stephen Victor Kosonocky ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/08 ,  G11C11/418 ,  G11C5/14 ,  G11C11/413 ,  G11C11/419

Abstract: A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.

公开(公告)号：US20200066677A1

公开(公告)日：2020-02-27

申请号：US16110678

申请日：2018-08-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind Bhagavat ,  David Hugh McIntyre ,  Rahul Agarwal

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.

公开(公告)号：US11011495B2

公开(公告)日：2021-05-18

申请号：US16110678

申请日：2018-08-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind Bhagavat ,  David Hugh McIntyre ,  Rahul Agarwal

IPC: H01L21/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H02M3/158 ,  H02M3/07

Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.

公开(公告)号：US20200090736A1

公开(公告)日：2020-03-19

申请号：US16132003

申请日：2018-09-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Alex Schaefer ,  Ravi Jotwani ,  David Hugh McIntyre

IPC: G11C11/419 ,  G11C11/418 ,  G11C5/14 ,  G11C7/12 ,  G11C7/10

Abstract: A write driver includes a first write data driver, a second write driver, and a control circuit. The first (second) write data driver provides a true (complement) write data signal to an output thereof at a high voltage when a true (complement) data signal is in a first logic state, at a ground voltage when the true (complement) data signal is in a second logic state and a negative bit line enable signal is inactive, and at a voltage below the ground voltage when the true (complement) data signal is in the second logic state and the negative bit line enable signal is active. The control circuit provides the negative bit line enable signal in an active state when a power supply voltage is below a first threshold, and in an inactive state when the power supply voltage is above a second threshold higher than the first threshold.

公开(公告)号：US20180226111A1

公开(公告)日：2018-08-09

申请号：US15424418

申请日：2017-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander W. Schaefer ,  Ravi T. Jotwani ,  Samiul Haque Khan ,  David Hugh McIntyre ,  Stephen Victor Kosonocky ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/08 ,  G06F3/06

CPC classification number: G11C8/08 ,  G11C5/145 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419

Abstract: A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.