公开(公告)号：US09494649B2

公开(公告)日：2016-11-15

申请号：US13731583

申请日：2012-12-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Arun S. Iyer ,  Prashanth Vallur ,  Shraddha Padiyar ,  Amit Govil

IPC: H03K5/14 ,  G01R31/317 ,  H03K5/1534 ,  H03K5/13

CPC classification number: G01R31/31726 ,  G01R31/31708 ,  H03K5/133 ,  H03K5/14 ,  H03K5/1534

Abstract: An integrated circuit (IC) measures uncertainties in a first signal. The IC comprises a programmable delay circuit to introduce a programmable delay to the first signal to generate a first delayed signal. The IC further comprises a digital delay line (DDL) comprising a first delay chain of delay elements having input to receive the first delayed signal. The DDL further comprises a set of storage elements, each storage element having an input coupled to an output of a corresponding delay element of the first delay chain, and an output to provide a corresponding bit of a digital reading. The DDL additionally comprises a decoder to generate a digital signature from the digital reading and a controller to iteratively adjust the programmed delay of the programmable delay circuit to search for a failure in a resulting digital signature.

Abstract translation: 集成电路（IC）测量第一个信号中的不确定性。 IC包括可编程延迟电路，以将可编程延迟引入第一信号以产生第一延迟信号。 IC还包括数字延迟线（DDL），其包括具有用于接收第一延迟信号的输入的延迟元件的第一延迟链。 DDL还包括一组存储元件，每个存储元件具有耦合到第一延迟链的相应延迟元件的输出的输入和用于提供数字读取的对应位的输出。 DDL还包括一个解码器，用于从数字读取中产生数字签名，控制器迭代地调整可编程延迟电路的编程延迟，以搜索所得到的数字签名中的故障。

公开(公告)号：US10247770B2

公开(公告)日：2019-04-02

申请号：US15381992

申请日：2016-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Abhay Deshpande ,  Arun S. Iyer ,  Prasanth K. Vallur ,  Girish Anathahally Singrigowda ,  Stephen V. Kosonocky

IPC: G01R31/26 ,  H03K5/159 ,  H03K3/03

Abstract: Various embodiments of a gate oxide breakdown detection technique detect gate oxide degradation due to stress on a per part basis without destroying functional circuits for an intended application. Stress on the gate oxide may be applied while nominal drain currents flow through a device, thereby stressing the device under conditions similar to actual operating conditions. The technique is relatively fast and does not require analog amplifiers or tuning of substantial amounts of other additional circuitry as compared to conventional gate oxide breakdown detection techniques.

公开(公告)号：US20140184243A1

公开(公告)日：2014-07-03

申请号：US13731583

申请日：2012-12-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Arun S. Iyer ,  Prashanth Vallur ,  Shraddha Padiyar ,  Amit Govil

IPC: G01R29/00

CPC classification number: G01R31/31726 ,  G01R31/31708 ,  H03K5/133 ,  H03K5/14 ,  H03K5/1534

Abstract: An integrated circuit (IC) measures uncertainties in a first signal. The IC comprises a programmable delay circuit to introduce a programmable delay to the first signal to generate a first delayed signal. The IC further comprises a digital delay line (DDL) comprising a first delay chain of delay elements having input to receive the first delayed signal. The DDL further comprises a set of storage elements, each storage element having an input coupled to an output of a corresponding delay element of the first delay chain, and an output to provide a corresponding bit of a digital reading. The DDL additionally comprises a decoder to generate a digital signature from the digital reading and a controller to iteratively adjust the programmed delay of the programmable delay circuit to search for a failure in a resulting digital signature.

Abstract translation: 集成电路（IC）测量第一个信号中的不确定性。 IC包括可编程延迟电路，以将可编程延迟引入第一信号以产生第一延迟信号。 IC还包括数字延迟线（DDL），其包括具有用于接收第一延迟信号的输入的延迟元件的第一延迟链。 DDL还包括一组存储元件，每个存储元件具有耦合到第一延迟链的相应延迟元件的输出的输入和用于提供数字读取的对应位的输出。 DDL还包括一个解码器，用于从数字读取中产生数字签名，控制器迭代地调整可编程延迟电路的编程延迟，以搜索所得到的数字签名中的故障。

公开(公告)号：US20180172753A1

公开(公告)日：2018-06-21

申请号：US15381992

申请日：2016-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Abhay Deshpande ,  Arun S. Iyer ,  Prasanth K. Vallur ,  Girish Anathahally Singrigowda ,  Stephen V. Kosonocky

IPC: G01R31/26 ,  H03K5/159 ,  H03K3/03

CPC classification number: G01R31/2623 ,  H03K3/0315 ,  H03K5/159

Abstract: Various embodiments of a gate oxide breakdown detection technique detect gate oxide degradation due to stress on a per part basis without destroying functional circuits for an intended application. Stress on the gate oxide may be applied while nominal drain currents flow through a device, thereby stressing the device under conditions similar to actual operating conditions. The technique is relatively fast and does not require analog amplifiers or tuning of substantial amounts of other additional circuitry as compared to conventional gate oxide breakdown detection techniques.