公开(公告)号：US20210373975A1

公开(公告)日：2021-12-02

申请号：US17029935

申请日：2020-09-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexandru DUTU ,  Matthew David SINCLAIR ,  Bradford BECKMANN ,  David A. WOOD

IPC: G06F9/52 ,  G06N20/00 ,  G06F11/30 ,  G06F11/34 ,  G06F9/46 ,  G06F9/30

Abstract: A processing system monitors and synchronizes parallel execution of workgroups (WGs). One or more of the WGs perform (e.g., periodically or in response to a trigger such as an indication of oversubscription) a waiting atomic instruction. In response to a comparison between an atomic value produced as a result of the waiting atomic instruction and an expected value, WGs that fail to produce a correct atomic value are identified as being in a waiting state (e.g., waiting for a synchronization variable). Execution of WGs in the waiting state is prevented (e.g., by a context switch) until corresponding synchronization variables are released.

公开(公告)号：US20240395289A1

公开(公告)日：2024-11-28

申请号：US18671854

申请日：2024-05-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh ADHINARAYANAN ,  Hyung-Dong LEE ,  Bradford BECKMANN ,  Seyedmohammad SEYEDZADEHDELCHEH ,  Sergey BLAGODUROV

IPC: G11C5/02 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: Integrated circuit (IC) memory devices and methods for fabricating the same are provided. In one example, an integrated circuit (IC) memory device is provided that includes a substrate, at least two or more memory (IC) dies, and a non-memory IC die integrated in a chip package. The memory (IC) dies are stacked on the substrate to form a memory die stack. The non-memory IC die contains row segmentation logic having an output routed to corresponding wordline drivers of the memory IC dies through vertical wiring passing through the memory die stack.

公开(公告)号：US20210191620A1

公开(公告)日：2021-06-24

申请号：US16724609

申请日：2019-12-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SeyedMohammad SEYEDZADEHDELCHEH ,  Xianwei ZHANG ,  Bradford BECKMANN ,  Shomit N. DAS

IPC: G06F3/06 ,  G06F12/0875

Abstract: In some embodiments, a memory controller in a processor includes a base value cache, a compressor, and a metadata cache. The compressor is coupled to the base value cache and the metadata cache. The compressor compresses a data block using at least a base value and delta values. The compressor determines whether the size of the data block exceeds a data block threshold value. Based on the determination of whether the size of the compressed data block generated by the compressor exceeds the data block threshold value, the memory controller transfers only a set of the compressed delta values to memory for storage. A decompressor located in the lower level cache of the processor decompresses the compressed data block using the base value stored in the base value cache, metadata stored in the metadata cache and the delta values stored in memory.

公开(公告)号：US20230229494A1

公开(公告)日：2023-07-20

申请号：US18095704

申请日：2023-01-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Muhammad Amber HASSAAN ,  Anirudh Mohan KAUSHIK ,  Sooraj PUTHOOR ,  Gokul Subramanian RAVI ,  Bradford BECKMANN ,  Ashwin AJI

IPC: G06F9/48 ,  G06F9/52 ,  G06F16/901

CPC classification number: G06F9/4881 ,  G06F9/52 ,  G06F16/9024 ,  G06F2209/486

Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.

公开(公告)号：US20210294646A1

公开(公告)日：2021-09-23

申请号：US16824601

申请日：2020-03-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Muhammad Amber HASSAAN ,  Anirudh Mohan KAUSHIK ,  Sooraj PUTHOOR ,  Gokul Subramanian RAVI ,  Bradford BECKMANN ,  Ashwin AJI

IPC: G06F9/48 ,  G06F16/901 ,  G06F9/52

Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.

公开(公告)号：US20220083233A1

公开(公告)日：2022-03-17

申请号：US17497286

申请日：2021-10-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Seyed Mohammad SEYEDZADEHDELCHEH ,  Xianwei ZHANG ,  Bradford BECKMANN ,  Shomit N. DAS

IPC: G06F3/06 ,  G06F12/0875

Abstract: In some embodiments, a memory controller in a processor includes a base value cache, a compressor, and a metadata cache. The compressor is coupled to the base value cache and the metadata cache. The compressor compresses a data block using at least a base value and delta values. The compressor determines whether the size of the data block exceeds a data block threshold value. Based on the determination of whether the size of the compressed data block generated by the compressor exceeds the data block threshold value, the memory controller transfers only a set of the compressed delta values to memory for storage. A decompressor located in the lower level cache of the processor decompresses the compressed data block using the base value stored in the base value cache, metadata stored in the metadata cache and the delta values stored in memory.

公开(公告)号：US20220066940A1

公开(公告)日：2022-03-03

申请号：US17007133

申请日：2020-08-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Johnathan ALSOP ,  Pouya FOTOUHI ,  Bradford BECKMANN ,  Sergey BLAGODUROV

IPC: G06F12/0891 ,  G06F12/0811 ,  G06F12/0882 ,  G06F9/30

Abstract: A processing system limits the propagation of unnecessary memory updates by bypassing writing back dirty cache lines to other levels of a memory hierarchy in response to receiving an indication from software executing at a processor of the processing system that the value of the dirty cache line is dead (i.e., will not be read again or will not be read until after it has been overwritten). In response to receiving an indication from software that data is dead, a cache controller prevents propagation of the dead data to other levels of memory in response to eviction of the dead data or flushing of the cache at which the dead data is stored.

公开(公告)号：US20200167191A1

公开(公告)日：2020-05-28

申请号：US16200503

申请日：2018-11-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Tsung Tai YEH ,  Bradford BECKMANN ,  Sooraj PUTHOOR ,  Matthew David SINCLAIR

IPC: G06F9/48

Abstract: A processing system includes a task queue, a laxity-aware task scheduler coupled to the task queue, and a workgroup dispatcher coupled to the laxity-aware task scheduler. Based on a laxity evaluation of laxity values associated with a plurality of tasks stored in the task queue, the workgroup dispatcher schedules the plurality of tasks. The laxity evaluation includes determining a priority of each task of the plurality of tasks. The laxity value is determined using laxity information, where the laxity information includes an arrival time, a task duration, a task deadline, and a number of workgroups.

公开(公告)号：US20200004586A1

公开(公告)日：2020-01-02

申请号：US16024244

申请日：2018-06-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexandru DUTU ,  Matthew David SINCLAIR ,  Bradford BECKMANN ,  David A. WOOD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: A first workgroup is preempted in response to threads in the first workgroup executing a first wait instruction including a first value of a signal and a first hint indicating a type of modification for the signal. The first workgroup is scheduled for execution on a processor core based on a first context after preemption in response to the signal having the first value. A second workgroup is scheduled for execution on the processor core based on a second context in response to preempting the first workgroup and in response to the signal having a second value. A third context it is prefetched into registers of the processor core based on the first hint and the second value. The first context is stored in a first portion of the registers and the second context is prefetched into a second portion of the registers prior to preempting the first workgroup.