公开(公告)号：US12204908B2

公开(公告)日：2025-01-21

申请号：US15997344

申请日：2018-06-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Marius Evers ,  Douglas Williams ,  Ashok T. Venkatachar ,  Sudherssen Kalaiselvan

IPC: G06F9/38 ,  G06F9/30

Abstract: A branch predictor predicts a first outcome of a first branch in a first block of instructions. Fetch logic fetches instructions for speculative execution along a first path indicated by the first outcome. Information representing a remainder of the first block is stored in response to the first predicted outcome being taken. In response to the first branch instruction being not taken, the branch predictor is restarted based on the remainder block. In some cases, entries corresponding to second blocks along speculative paths from the first block are accessed using an address of the first block as an index into a branch prediction structure. Outcomes of branch instructions in the second blocks are concurrently predicted using a corresponding set of instances of branch conditional logic and the predicted outcomes are used in combination with the remainder block to restart the branch predictor in response to mispredictions.

公开(公告)号：US12222797B2

公开(公告)日：2025-02-11

申请号：US18084499

申请日：2022-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： James Mossman ,  Robert Cohen ,  Sudherssen Kalaiselvan ,  Tzu-Wei Lin

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F1/3296

Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240201777A1

公开(公告)日：2024-06-20

申请号：US18084499

申请日：2022-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： James Mossman ,  Robert Cohen ,  Sudherssen Kalaiselvan ,  Tzu-Wei Lin

IPC: G06F1/3296 ,  G06F1/3287

CPC classification number: G06F1/3296 ,  G06F1/3287

Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11907126B2

公开(公告)日：2024-02-20

申请号：US17116950

申请日：2020-12-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert B. Cohen ,  Tzu-Wei Lin ,  Anthony J. Bybell ,  Sudherssen Kalaiselvan ,  James Mossman

IPC: G06F9/38 ,  G06F12/0855

CPC classification number: G06F12/0855 ,  G06F9/3808 ,  G06F9/3814 ,  G06F2212/60

Abstract: A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.