公开(公告)号：US20170222030A1

公开(公告)日：2017-08-03

申请号：US15479022

申请日：2017-04-04

Applicant: Agency for Science, Technology and Research

Inventor： Lakshmi Kanta Bera ,  Surani Bin Dolmanan ,  Manippady Krishna Kumar ,  Rasanayagam Sivasayan Kajen ,  Sudhiranjan Tripathy

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/283 ,  H01L21/324 ,  H01L21/311 ,  H01L21/308 ,  H01L29/45 ,  H01L21/02

CPC classification number: H01L29/7783 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/3085 ,  H01L21/31133 ,  H01L21/324 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/7786 ,  H01L29/78

Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a first and a second nucleation layer on a substrate; depositing a binary layer over these nucleation layers; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.

公开(公告)号：US09954088B2

公开(公告)日：2018-04-24

申请号：US15029835

申请日：2014-10-20

Applicant: Agency for Science, Technology and Research

Inventor： Lakshmi Kanta Bera ,  Surani Bin Dolmanan ,  Manippady Krishna Kumar ,  Rasanayagam Sivasayan Kajen ,  Sudhiranjan Tripathy

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L29/45 ,  H01L21/283 ,  H01L21/308 ,  H01L21/311 ,  H01L21/324 ,  H01L21/02 ,  H01L29/417

CPC classification number: H01L29/7783 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/3085 ,  H01L21/31133 ,  H01L21/324 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/7786 ,  H01L29/78

Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a nucleation layer on a substrate; depositing a binary layer over the nucleation layer; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge or their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.

公开(公告)号：US09972709B2

公开(公告)日：2018-05-15

申请号：US15479022

申请日：2017-04-04

Applicant: Agency for Science, Technology and Research

Inventor： Lakshmi Kanta Bera ,  Surani Bin Dolmanan ,  Manippady Krishna Kumar ,  Rasanayagam Sivasayan Kajen ,  Sudhiranjan Tripathy

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L29/45 ,  H01L21/283 ,  H01L21/308 ,  H01L21/311 ,  H01L21/324 ,  H01L21/02 ,  H01L29/417

CPC classification number: H01L29/7783 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/3085 ,  H01L21/31133 ,  H01L21/324 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/7786 ,  H01L29/78

Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a first and a second nucleation layer on a substrate; depositing a binary layer over these nucleation layers; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.