公开(公告)号：US07510981B2

公开(公告)日：2009-03-31

申请号：US11542219

申请日：2006-10-04

申请人： Akira Mitsuiki ,  Tomoo Nakayama ,  Osamu Fujita

发明人： Akira Mitsuiki ,  Tomoo Nakayama ,  Osamu Fujita

IPC分类号： H01L21/302

CPC分类号： H01L21/76224

摘要： A semiconductor device includes an element isolation film, which exhibits less variations in the height dimension from the surface of the substrate and has a desired height dimension from the surface of the substrate. A process for manufacturing a semiconductor device includes: providing a predetermined pattern of a silicon nitride film and a protective film which covers the silicon nitride film, on a semiconductor substrate; selectively etching the semiconductor substrate using the protective film as a mask to form a trenched portion; removing the protective film to expose the silicon nitride film; depositing an element isolation film, so as to fill the trenched portion therewith and cover the silicon nitride film; removing the element isolation film formed on the silicon nitride film by polishing thereof until the silicon nitride film is exposed; and removing the silicon nitride film.

摘要翻译： 半导体器件包括元件隔离膜，该元件隔离膜在与衬底表面的高度尺寸上的变化较小，并且具有从衬底表面所需的高度尺寸。 一种制造半导体器件的方法包括：在半导体衬底上提供氮化硅膜的预定图案和覆盖氮化硅膜的保护膜; 使用保护膜作为掩模选择性地蚀刻半导体衬底以形成沟槽部分; 去除保护膜以暴露氮化硅膜; 沉积元件隔离膜，以便用其填充沟槽部分并覆盖氮化硅膜; 通过研磨除去在氮化硅膜上形成的元件隔离膜，直到氮化硅膜露出为止; 并除去氮化硅膜。

公开(公告)号：US20070087520A1

公开(公告)日：2007-04-19

申请号：US11542219

申请日：2006-10-04

申请人： Akira Mitsuiki ,  Tomoo Nakayama ,  Osamu Fujita

发明人： Akira Mitsuiki ,  Tomoo Nakayama ,  Osamu Fujita

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A semiconductor device includes an element isolation film, which exhibits less variations in the height dimension from the surface of the substrate and has a desired height dimension from the surface of the substrate. A process for manufacturing a semiconductor device includes: providing a predetermined pattern of a silicon nitride film and a protective film which covers the silicon nitride film, on a semiconductor substrate; selectively etching the semiconductor substrate using the protective film as a mask to form a trenched portion; removing the protective film to expose the silicon nitride film; depositing an element isolation film, so as to fill the trenched portion therewith and cover the silicon nitride film; removing the element isolation film formed on the silicon nitride film by polishing thereof until the silicon nitride film is exposed; and removing the silicon nitride film.

摘要翻译： 半导体器件包括元件隔离膜，该元件隔离膜在与衬底表面的高度尺寸上的变化较小，并且具有从衬底表面所需的高度尺寸。 一种制造半导体器件的方法包括：在半导体衬底上提供氮化硅膜的预定图案和覆盖氮化硅膜的保护膜; 使用保护膜作为掩模选择性地蚀刻半导体衬底以形成沟槽部分; 去除保护膜以暴露氮化硅膜; 沉积元件隔离膜，以便用其填充沟槽部分并覆盖氮化硅膜; 通过研磨除去在氮化硅膜上形成的元件隔离膜，直到氮化硅膜露出为止; 并除去氮化硅膜。

公开(公告)号：US20080194107A1

公开(公告)日：2008-08-14

申请号：US12068305

申请日：2008-02-05

申请人： Akira Mitsuiki ,  Atsuro Inada

发明人： Akira Mitsuiki ,  Atsuro Inada

IPC分类号： H01L21/311

CPC分类号： H01L21/3081 ,  H01L21/0206 ,  H01L21/76224

摘要： The present invention aims to improve the controllability of dimensions at the time when a silicon substrate or a film formed on top of the silicon substrate is etched. For this purpose, a SiN film is formed so as to be in contact with the top of an element-forming surface of a silicon substrate, and the SiN film is selectively removed to form an opening portion. Then, a plasma processing is carried out on the element-forming surface of the silicon substrate to remove deposits attached on sidewalls of the opening portion formed in the SiN film. After that, the silicon substrate is selectively removed by using the SiN film as a mask to form a concave portion in the silicon substrate.

摘要翻译： 本发明的目的在于提高在硅衬底或形成在硅衬底上的膜被蚀刻时的尺寸的可控性。 为此，形成SiN膜以与硅衬底的元件形成表面的顶部接触，并且选择性地去除SiN膜以形成开口部。 然后，在硅衬底的元件形成表面上进行等离子体处理，以除去附着在形成于SiN膜中的开口部分的侧壁上的沉积物。 之后，通过使用SiN膜作为掩模来选择性地除去硅衬底，以在硅衬底中形成凹部。

公开(公告)号：US06716761B2

公开(公告)日：2004-04-06

申请号：US10023847

申请日：2001-12-21

申请人： Akira Mitsuiki

发明人： Akira Mitsuiki

IPC分类号： H01L21302

CPC分类号： H01L21/32139 ,  H01L21/32137

摘要： A resist pattern is formed on a film to be processed using a lithography technique. The line width of the resist pattern is narrowed using a slimming technique. Thereafter, the pattern of a first film to be processed is formed in the space that has been widened by slimming, utilizing the phenomenon in which anisotropic etching under a reduced pressure accelerates the etching rate in the vicinity of the side of the line of the pattern compared to other areas. An underlying second film to be processed is etched using the first film to be processed as a mask. Thereby the pattern of the second film to be processed that has a pitch ½ the lithography pattern is formed.

摘要翻译： 使用光刻技术在待加工的膜上形成抗蚀剂图案。 使用减肥技术使抗蚀剂图案的线宽变窄。 此后，通过减肥加宽加工的空间，形成第一被处理膜的图案，利用减压下的各向异性蚀刻加速图案线侧附近的蚀刻速度的现象 与其他地区相比。 使用待处理的第一膜作为掩模蚀刻待处理的下层第二膜。 从而形成具有光刻图案间距1/2的待处理第二膜的图案。

公开(公告)号：US08492227B2

公开(公告)日：2013-07-23

申请号：US12837901

申请日：2010-07-16

申请人： Akira Mitsuiki ,  Atsuro Inada

发明人： Akira Mitsuiki ,  Atsuro Inada

IPC分类号： H01L21/8234 ,  H01L21/311

CPC分类号： H01L21/823468 ,  H01L29/6653 ,  H01L29/6656

摘要： An etching stopper film is formed over a first insulating film. Then, a second insulating film is formed with a thickness that allows concave and convex portions formed due to a first gate electrode to remain. Then, anisotropic etching is performed using the etching stopper film as a stopper to remove the second insulating film over a second gate electrode and form a first side wall spacer of the first gate electrode. Then, the etching stopper film is removed. Then, anisotropic etching is performed on the first insulating film to form a second side wall spacer over the second gate electrode and form a third side wall spacer which is disposed inside the first side wall spacer over the first gate electrode.

摘要翻译： 在第一绝缘膜上形成蚀刻停止膜。 然后，形成第二绝缘膜，其厚度允许残留由第一栅电极形成的凹凸部分。 然后，使用蚀刻阻挡膜作为阻挡层进行各向异性蚀刻，以在第二栅电极上除去第二绝缘膜，并形成第一栅电极的第一侧壁间隔物。 然后，去除蚀刻停止膜。 然后，对第一绝缘膜进行各向异性蚀刻，以在第二栅电极上形成第二侧壁间隔物，并形成第三侧壁间隔物，该第三侧壁隔离物设置在第一栅电极上的第一侧壁隔离物的内侧。

公开(公告)号：US06376383B2

公开(公告)日：2002-04-23

申请号：US09233089

申请日：1999-01-19

申请人： Akira Mitsuiki

发明人： Akira Mitsuiki

IPC分类号： H01L213065

CPC分类号： H01L21/3065 ,  H01L21/32137

摘要： A gate oxide film and a polysilicon layer are formed on a silicon substrate, and a pattern of photoresist is formed on the polysilicon layer. A silicon layer is etched halfway using a CF type gas such as CF4, CHF3, CH2F2 and C4F8 or a mixed gas including the same with the photoresist serving as a mask. This leaves fluorocarbon type deposition on sides of the etched hole. Then, any residue of the silicon film is etched using the gas of Cl2, HBr, SF6 or O2. This makes it possible to provide a configuration having inclined sides after etching.

摘要翻译： 在硅衬底上形成栅极氧化膜和多晶硅层，并且在多晶硅层上形成光致抗蚀剂图案。 使用诸如CF 4，CHF 3，CH 2 F 2和C 4 F 8的CF型气体或包含该硅层的光致抗蚀剂作为掩模的混合气体半中蚀刻硅层。 这样会在蚀刻孔的侧面留下碳氟化合物类型的沉积。 然后，使用Cl2，HBr，SF6或O2的气体蚀刻硅膜的任何残留物。 这使得可以提供在蚀刻之后具有倾斜侧面的构造。

公开(公告)号：US07462566B2

公开(公告)日：2008-12-09

申请号：US11600071

申请日：2006-11-16

申请人： Masato Fujita ,  Kensuke Taniguchi ,  Akira Mitsuiki

发明人： Masato Fujita ,  Kensuke Taniguchi ,  Akira Mitsuiki

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28035

摘要： In the process of forming a predetermined pattern in a process target film, a stacked hard mask film having a first film, a second film and a third film stacked in this order is formed on the process target film (S100), fine line patterns are formed in the third film through a fine-pattern-forming resist film while using the second film as an etching stopper (S102), and the fine-pattern-forming resist film is removed (S104). Subsequently, light exposure is carried out using a resist film (S106 to S110), and the second film, the first film and the process target film are then selectively dry-etched in a sequential manner, to thereby form the process target film into a predetermined pattern (S112). The first film remained on the process target film is then removed (S114).

摘要翻译： 在处理目标薄膜中形成预定图案的过程中，在处理目标薄膜上形成具有第一薄膜，第二薄膜和第三薄膜的层叠的硬掩模薄膜（S100），细线图案是 通过精细图案形成抗蚀剂膜形成在第三膜中，同时使用第二膜作为蚀刻停止层（S102），除去微细图案形成抗蚀剂膜（S104）。 随后，使用抗蚀剂膜进行曝光（S106〜S110），然后依次对第二膜，第一膜和处理对象膜进行选择性干蚀刻，从而将处理目标膜形成为 预定图案（S112）。 然后，将残留在处理目标膜上的第一膜除去（S114）。

公开(公告)号：US06372602B1

公开(公告)日：2002-04-16

申请号：US09571733

申请日：2000-05-15

申请人： Akira Mitsuiki

发明人： Akira Mitsuiki

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/0334 ,  H01L21/0335 ,  H01L21/3083 ,  H01L21/3085

摘要： The present invention provides a method of forming a shallow trench isolation structure in a substrate. The method comprises the steps of: forming an isolation silicon oxide film which comprises an upper portion extending over a silicon oxide film over a silicon nitride film and a lower portion extending in a trench in a silicon substrate; and carrying out an isotropic etching to said upper portion of said isolation silicon oxide film and said silicon oxide film, thereby forming an isolation trench structure without divots in said trench in said silicon substrate.

摘要翻译： 本发明提供一种在衬底中形成浅沟槽隔离结构的方法。 该方法包括以下步骤：形成隔离氧化硅膜，该隔离氧化硅膜包括在氮化硅膜上延伸超过氧化硅膜的上部和在硅衬底中的沟槽中延伸的下部; 对所述隔离氧化硅膜和所述氧化硅膜的所述上部进行各向同性蚀刻，从而在所述硅衬底的所述沟槽中形成无凹坑的隔离沟道结构。

公开(公告)号：US20080085608A1

公开(公告)日：2008-04-10

申请号：US11600071

申请日：2006-11-16

申请人： Masato Fujita ,  Kensuke Taniguchi ,  Akira Mitsuiki

发明人： Masato Fujita ,  Kensuke Taniguchi ,  Akira Mitsuiki

IPC分类号： H01L21/31

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28035

摘要： In the process of forming a predetermined pattern in a process target film, a stacked hard mask film having a first film, a second film and a third film stacked in this order is formed on the process target film (S100), fine line patterns are formed in the third film through a fine-pattern-forming resist film while using the second film as an etching stopper (S102), and the fine-pattern-forming resist film is removed (S104). Subsequently, light exposure is carried out using a resist film (S106 to S110), and the second film, the first film and the process target film are then selectively dry-etched in a sequential manner, to thereby form the process target film into a predetermined pattern (S112). The first film remained on the process target film is then removed (S114).

摘要翻译： 在处理目标薄膜中形成预定图案的过程中，在工艺目标薄膜（S100）上形成具有第一薄膜，第二薄膜和第三薄膜的层叠的硬掩膜， 通过精细图案形成抗蚀剂膜形成在第三膜中，同时使用第二膜作为蚀刻停止层（S102），除去微细图案形成抗蚀剂膜（S104）。 随后，使用抗蚀剂膜（S106〜S110）进行曝光，然后依次对第二膜，第一膜和处理对象膜进行选择性干蚀刻，从而形成处理对象膜 变成预定图案（S112）。 然后将剩余在工艺靶膜上的第一膜除去（S114）。

公开(公告)号：US06200902B1

公开(公告)日：2001-03-13

申请号：US09050944

申请日：1998-03-31

申请人： Akira Mitsuiki

发明人： Akira Mitsuiki

IPC分类号： H01L21302

CPC分类号： H01L21/32137

摘要： In the process of simultaneously etching a polysilicon layer in a groove of a memory cell section and a polysilicon layer in a peripheral circuit section, a Cl2/HBr-based gas is used as a first etching step, and this etching is performed until polysilicon in the peripheral section is removed. Next, the gas is switched to a C12/HBr/O2-based gas to remove an etched particulate resist film having accumulated in the groove. As a final step, the polysilicon layer remaining in the groove is etched with a HBr/O2-based gas having a high selectivity ratio against an oxide film.

摘要翻译： 在同时蚀刻存储单元部分的槽中的多晶硅层和外围电路部分中的多晶硅层的过程中，使用Cl 2 / HBr基气体作为第一蚀刻步骤，并且进行该蚀刻直到多晶硅 外围部分被去除。 接下来，将气体切换到基于C12 / HBr / O2的气体，以去除积聚在凹槽中的蚀刻的颗粒状抗蚀剂膜。 作为最后一步，用对氧化膜具有高选择比的HBr / O 2基气体蚀刻留在槽中的多晶硅层。