公开(公告)号：US08356124B1

公开(公告)日：2013-01-15

申请号：US10846386

申请日：2004-05-14

申请人： Almir Davis ,  Michael Sgrosso ,  William F. Baxter, III ,  Avinash Kallat

发明人： Almir Davis ,  Michael Sgrosso ,  William F. Baxter, III ,  Avinash Kallat

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F13/368 ,  G06F13/14 ,  H04L12/40

CPC分类号： G06F13/362

摘要： A data transfer system includes a PCI Express transaction layer having an input for serially receiving posted and non-posted request packets and completion packets; an application layer coupled to the PCI Express transaction layer for receiving posted and non-posted request packets and completion packets from the PCI Express transaction layer; a first transmission interface coupling the application layer to the PCI Express transaction layer; and a second transmission interface coupling the application layer to the PCI Express transaction layer. The PCI Express transaction layer transmits posted and non-posted request packets to the application layer over the first transmission interface and transmits completion packets to the application layer over the second transmission interface.

摘要翻译： 数据传输系统包括具有用于串行接收发布和未发布的请求分组和完成分组的输入的PCI Express事务层; 耦合到PCI Express事务层的应用层，用于从PCI Express事务层接收发布和未发布的请求分组和完成分组; 将应用层耦合到PCI Express事务层的第一传输接口; 以及将应用层耦合到PCI Express事务层的第二传输接口。 PCI Express事务层通过第一传输接口将发布和未发布的请求数据包发送到应用层，并通过第二个传输接口将完成数据包发送到应用层。

公开(公告)号：US07073031B1

公开(公告)日：2006-07-04

申请号：US10740343

申请日：2003-12-18

申请人： Christopher S. MacLellan ,  Avinash Kallat ,  Almir Davis ,  Stephen L. Scaringella

发明人： Christopher S. MacLellan ,  Avinash Kallat ,  Almir Davis ,  Stephen L. Scaringella

IPC分类号： G06F12/00

CPC分类号： G06F9/52

摘要： A system for maintaining data coherency. The system includes a plurality of processors. A plurality of resources is also included. One portion of the resources is sharable with the plurality of processors and each one of the other ones of the resources being dedicated to a predetermined one of the processors. The system also includes a plurality of buffers. Each one of the buffers is associated with a corresponding one of the plurality of processors. Each one of the buffers is adapted to successively store information presented thereto in successive locations of such one of the buffers. The information includes requests from the corresponding one of the processor. The system includes a logic section responsive to each one of the requests provided by the plurality of processors. The logic section produces indicia indicating whether or not such one of the requests is a request for an operation with one of the sharable resources. The logic section inserts the indicia into a succeeding one of the locations of the buffers associated with such one of the processor providing such one of the requests. The logic section also simultaneously inserts such indicia into a next succeeding available location of the other ones of the plurality of buffers. The logic section inhibits execution of requests in the buffers stored in locations thereof succeeding the location having stored therein any such inserted indicia.

摘要翻译： 用于维护数据一致性的系统。 该系统包括多个处理器。 还包括多个资源。 资源的一部分与多个处理器共享，并且其中一个资源中的每一个专用于预定的一个处理器。 该系统还包括多个缓冲器。 每个缓冲器与多个处理器中的相应一个处理器相关联。 缓冲器中的每一个适于在这些缓冲器的连续位置中连续存储呈现给它的信息。 该信息包括来自相应处理器之一的请求。 该系统包括响应于由多个处理器提供的每个请求的逻辑部分。 逻辑部分产生指示这样的一个请求是否是具有可共享资源之一的操作的请求的标记。 逻辑部分将标记插入与提供这种请求之一的处理器之一相关联的缓冲器的后续位置之一。 逻辑部分还同时将这样的标记插入到多个缓冲器中的其他缓冲器的下一个后续可用位置。 逻辑部分禁止存储在其中存储有任何这样的插入标记的位置的位置中的缓冲器中的请求的执行。

公开(公告)号：US07398339B1

公开(公告)日：2008-07-08

申请号：US11645334

申请日：2006-12-26

申请人： Almir Davis ,  David Iwatsuki ,  Matthew Sullivan

发明人： Almir Davis ,  David Iwatsuki ,  Matthew Sullivan

IPC分类号： G06F3/00

CPC分类号： G06F13/4059

摘要： A system for transferring data packets between a data packet transfer core and a number of clients of an application layer, including an interface between the data packet transfer core and the application layer for transferring data packets from the packet transfer core to a first client and a second client. The data packet transfer core includes a number of core buffers for receiving data packet transfers input to the data packet transfer core. Each of the number of core buffers include a cut-through data path including a register and a bypass data path, the bypass data path transferring data packets from an input to the register to an output of the register without passing through the register. The system further includes a first data path from the first interface to the first client and a second data path from the interface to the second client, the second data path including an application layer buffer having an input coupled to the interface and an output coupled to the second client, the application layer buffer being for storing data packets transmitted to the second client when data packets are transmitted to the second client at a rate that is faster than the second client is able to receive the data packets. In a first mode of operation, data packets transmitted from the data packet transfer core to the first client are transferred through the bypass data path of at least one of the number of core buffers, over the interface and directly to the first client over the first data path.

摘要翻译： 一种用于在数据分组传送核心和应用层的多个客户机之间传送数据分组的系统，包括数据分组传送核心和用于将数据分组从分组传送核心传送到第一客户端的应用层之间的接口，以及 第二客户端 数据分组传送核心包括用于接收输入到数据分组传送核心的数据分组传输的多个核心缓冲器。 核心缓冲器中的每一个包括包括寄存器和旁路数据路径的直通数据路径，旁路数据路径将数据分组从输入传送到寄存器到寄存器的输出，而不通过寄存器。 该系统还包括从第一接口到第一客户机的第一数据路径和从接口到第二客户端的第二数据路径，第二数据路径包括具有耦合到接口的输入的应用层缓冲器，以及耦合到 第二客户机，当以比第二客户端更快的速率向第二客户端发送数据分组时，用于存储发送到第二客户端的数据分组的应用层缓冲器能够接收数据分组。 在第一操作模式中，从数据分组传送核心传输到第一客户机的数据分组通过接口的数量的核心缓冲器中的至少一个的旁路数据路径传送，并通过第一模式直接传送到第一客户端 数据路径。

公开(公告)号：US07219175B1

公开(公告)日：2007-05-15

申请号：US11095099

申请日：2005-03-31

申请人： Almir Davis ,  David Iwatsuki ,  Matthew Sullivan

发明人： Almir Davis ,  David Iwatsuki ,  Matthew Sullivan

IPC分类号： G06F13/42

CPC分类号： G06F13/4059

摘要： A system for transferring packets between a packet transfer core and an application layer device over an application layer interface includes a buffer system disposed in the packet transfer core having an input for receiving packets from a packet source; an output for transferring packets to the application layer interface; a buffer device having an input coupled to the input of the buffer system and an output; a selection device having a first input coupled to the output of the buffer device, a control input and an output coupled to the output of the buffer system; and a bypass path coupled between the input of the buffer system and a second input of the selection device. The control input of the selection device receives a first wait signal from the application layer device which is not asserted in a first mode of operation and asserted in a second mode of operation. In the first mode of operation, packets are transferred from the input of the buffer system to the output of the buffer system via the bypass path and, in the second mode of operation, packets are transferred from the input of the buffer system to the buffer device, and are store in the buffer device without being transferred to the output of the buffer system until the first wait signal from the application layer device is deasserted.

摘要翻译： 通过应用层接口在分组传输核心和应用层设备之间传送分组的系统包括设置在分组传送核心中的缓冲器系统，其具有用于从分组源接收分组的输入; 用于将数据包传送到应用层接口的输出; 具有耦合到所述缓冲器系统的输入的输入和输出的缓冲器装置; 选择装置，其具有耦合到所述缓冲装置的输出的第一输入，耦合到所述缓冲系统的输出的控制输入和输出; 以及耦合在缓冲器系统的输入和选择装置的第二输入之间的旁路路径。 选择设备的控制输入从应用层设备接收第一等待信号，该第一等待信号在第一操作模式中未被确认并在第二操作模式中被断言。 在第一操作模式中，分组经由旁路路径从缓冲系统的输入端传送到缓冲系统的输出，在第二操作模式中，分组从缓冲系统的输入传送到缓冲器 设备，并且存储在缓冲设备中，而不会被传送到缓冲系统的输出，直到来自应用层设备的第一等待信号被断言为止。

公开(公告)号：US07400672B1

公开(公告)日：2008-07-15

申请号：US10905393

申请日：2004-12-30

申请人： Almir Davis ,  Jeffrey S. Kinne ,  Christopher S. MacLellan ,  Stephen L. Scaringella

发明人： Almir Davis ,  Jeffrey S. Kinne ,  Christopher S. MacLellan ,  Stephen L. Scaringella

IPC分类号： H04L15/16 ,  H04J3/16

CPC分类号： H04L1/0045 ,  H04L2001/0094

摘要： A system for detecting transmission errors in a data transmission system includes a receiver for receiving a data packet transmitted thereto by a corresponding transmitter and transmitting the data packet to a destination device and an error detection device for receiving a plurality of protocol signals that control the operation of the transmitter and the receiver. The error detection device applies at least one predetermined rule to the protocol signals, wherein a violation of the at least one rule by the protocol signals indicates that an error in the transmission of the packet has occurred, and asserts an error signal when the at least one rule has been violated by the protocol signals. The system further includes a packet filtering device coupled to receive the error signal from the error detection device and the data packet from the receiver, wherein, upon receiving the asserted error signal, the packet filtering device terminates the transmission of the data packet to the destination device.

摘要翻译： 一种用于检测数据传输系统中的传输错误的系统，包括：接收机，用于接收由相应的发射机发射的数据分组，并将数据分组发送到目的设备;以及错误检测设备，用于接收控制该操作的多个协议信号 的发射机和接收机。 误差检测装置对协议信号应用至少一个预定规则，其中由协议信号违反至少一个规则指示已经发生了分组的传输中的错误，并且当至少发出了错误信号 一个规则被协议信号所违反。 该系统还包括一个分组过滤装置，它被耦合以从误差检测装置接收错误信号和从接收机接收数据分组，其中，在接收到断言的误差信号时，分组过滤装置终止数据分组到目的地的传输 设备。

公开(公告)号：US07243177B1

公开(公告)日：2007-07-10

申请号：US11095420

申请日：2005-03-31

申请人： Almir Davis ,  David Iwatsuki ,  Matthew Sullivan

发明人： Almir Davis ,  David Iwatsuki ,  Matthew Sullivan

IPC分类号： G06F13/42 ,  G06F13/00 ,  G08C15/00 ,  H04L12/54

CPC分类号： H04L47/10 ,  H04L47/266 ,  H04L47/30

摘要： A system for controlling packet transfers includes a packet transfer core; an application layer coupled to the packet transfer core by an application interface; a buffer in the packet transfer core for receiving packets from a packet source and transferring the packets to the application layer over the application interface, the packets comprising one or more words; a register in the application layer for receiving packets from the application interface; and a client device for receiving packets transferred thereto from the register. When the client is unable to receive packets from the register, the client asserts a first wait signal to the register, causing the register to continue receiving packets from the interface and storing the packets without transferring the packets to the client. When the register is unable to continue receiving packets from the interface, the register asserts a second wait signal to the buffer over the application interface, causing the buffer to continue receiving packets from the packet source and storing the packets without transferring packets to the interface.

摘要翻译： 用于控制分组传送的系统包括分组传送核心; 通过应用接口耦合到所述分组传送核心的应用层; 分组传送核心中的缓冲器，用于从分组源接收分组，并通过应用接口将分组传送到应用层，分组包括一个或多个单词; 应用层中的寄存器，用于从应用接口接收数据包; 以及用于从寄存器接收从其传送的分组的客户端设备。 当客户端不能从寄存器接收到数据包时，客户端向该寄存器发出一个第一个等待信号，导致该寄存器继续接收来自该接口的数据包，并存储该数据包而不将数据包传送给客户端。 当寄存器不能从接口继续接收数据包时，该寄存器通过应用接口向缓冲器发出第二个等待信号，导致缓冲区继续从分组源接收数据包，并存储数据包，而不会将数据包传输到接口。

公开(公告)号：US08270322B1

公开(公告)日：2012-09-18

申请号：US10905391

申请日：2004-12-30

申请人： Almir Davis ,  Jeffrey S. Kinne ,  Christopher S. MacLellan ,  Stephen L. Scaringella

发明人： Almir Davis ,  Jeffrey S. Kinne ,  Christopher S. MacLellan ,  Stephen L. Scaringella

IPC分类号： H04J1/16

CPC分类号： G06F13/4217

摘要： A system for arbitrating a transmission of data includes a number K of transmitters, a request signal transmission device, a device valid signal transmission device, and a data valid logic device, wherein a transmitter asserts a request signal to request permission to begin a data transmission and transmits transmission-identifying information to a receiver. The data valid logic device deasserts a data valid signal based on the state of a wait signal, thereby preventing a transmission of data from each of the K transmitters at one clock cycle after a clock cycle at which the data signal is deasserted. An arbitration logic device of the receiver selects one of the number K of transmitters to grant permission to transmit data to the receiver and outputs an arbitration signal to a wait logic device instructing the wait logic device to deassert the wait signal of the selected trnasmitter.

摘要翻译： 用于仲裁数据传输的系统包括发射机数量K，请求信号传输设备，设备有效信号传输设备和数据有效逻辑设备，其中发射机断言请求信号以请求开始数据传输的许可 并将发送识别信息发送到接收机。 数据有效逻辑装置根据等待信号的状态取消数据有效信号，从而防止在数据信号被断言的时钟周期之后的一个时钟周期从每个K个发射机发送数据。 接收机的仲裁逻辑设备选择发射机数量K中的一个，以允许向接收机发送数据的许可，并将仲裁信号输出到等待逻辑装置，指示等待逻辑装置取消所选择的发射机的等待信号。

公开(公告)号：US07675929B1

公开(公告)日：2010-03-09

申请号：US11324352

申请日：2006-01-03

申请人： Almir Davis

发明人： Almir Davis

IPC分类号： H04L12/56

CPC分类号： H04L47/10 ,  H04L49/505

摘要： A data flow management system and method in which an application and its clients are made aware of the available credits for each type of transfer before the transfer is attempted. This enables the clients to transmit packets only when the RX side has issued a sufficient number of credits to insure that the transmission will not be stalled. The invention eliminates the need for FIFO buffers in the PCI-Express core, since the application will not transmit packets to the core until the required number of credits for the particular transfer type is available. Therefore, packet transmissions do not require buffering in the core, as they are only sent when they can be sent all the way through the core to the link. The efficient back-to-back transfer support enabled by this protocol increases the overall throughput and efficiency of the system as transfers through the application interface have fewer gaps therebetween, because the credit management protocol with its back-to-back feature reduces the idle times between packets traversing the application interface. An enhanced Quality of Service feature is also introduced by creating an environment where the low-latency packets can receive a highest attention and the lowest transmission wait time.

摘要翻译： 一种数据流管理系统和方法，其中在尝试转移之前，使应用程序及其客户端知道每种类型的传输的可用信用。 这使得客户端仅在RX侧已经发出足够数量的信用以确保传输不会被停止时才传输分组。 本发明消除了对PCI-Express核心中的FIFO缓冲器的需要，因为在特定传输类型所需的数量可用的情况下，应用程序将不会将数据包传输到核心。 因此，分组传输不需要在核心中进行缓冲，因为它们只有当它们可以一直通过核心发送到链路时被发送。 由于具有背靠背功能的信用管理协议减少了空闲时间，因此通过该协议实现的高效的背对背传输支持增加了系统的整体吞吐量和效率，因为通过应用接口的传输具有较小的间隙， 在穿过应用程序接口的数据包之间。 通过创建低延迟分组可以获得最高关注度和最低传输等待时间的环境，还引入了增强的服务质量特性。

公开(公告)号：US07254654B1

公开(公告)日：2007-08-07

申请号：US10813989

申请日：2004-04-01

申请人： Almir Davis ,  Christopher S. MacLellan

发明人： Almir Davis ,  Christopher S. MacLellan

IPC分类号： G06F3/00

CPC分类号： G06F3/0656 ,  G06F3/0613 ,  G06F3/0676

摘要： A data transfer device is disclosed for writing data to and reading data from a disk drive system through a plurality of ports of the data transfer device. The data transfer device includes a first buffer for serially receiving, from a host system, control portions of data read requests and data write transfers; a second buffer for serially receiving, from the host system, data portions of data write transfers received by the first buffer; and N temporary storage devices, wherein N is a positive integer, coupled to the first buffer and the second buffer, the N temporary storage devices for parallelly receiving and temporarily storing consecutive control portions of the data read transfers and data write transfers from the first buffer. Up to N of the data read transfers and data write transfers are transferred to the disk drive system through the plurality of ports simultaneously.

摘要翻译： 公开了一种数据传输装置，用于通过数据传送装置的多个端口将数据写入和读取来自磁盘驱动器系统的数据。 数据传送装置包括：第一缓冲器，用于从主机系统串行地接收数据读取请求和数据写入传送的控制部分; 用于从所述主机系统串行地接收由所述第一缓冲器接收的数据写入传输的数据部分的第二缓冲器; N个临时存储装置，其中N是正整数，耦合到第一缓冲器和第二缓冲器，N个临时存储装置用于并行地接收和临时存储来自第一缓冲器的数据读取传送和数据写入传输的连续控制部分 。 最多N个数据读取传输和数据写入传输通过多个端口同时传输到磁盘驱动器系统。

公开(公告)号：US08140728B1

公开(公告)日：2012-03-20

申请号：US13079409

申请日：2011-04-04

申请人： Almir Davis

发明人： Almir Davis

IPC分类号： G06F13/368 ,  G06F12/00

CPC分类号： H04L29/06

摘要： A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data transfers are routed through the system based on arbitration logic that prioritizes by function in a primary arbitration stage and by client in a subsequent arbitration stage.

摘要翻译： 描述了用于将数据传输从多个客户机路由到数据传输线路的数据分组仲裁系统。 该系统包括用于将数据从多个客户端传送到数据传输线路的多个仲裁阶段。 数据传输通过系统基于仲裁逻辑进行路由，仲裁逻辑通过主要仲裁阶段中的功能和客户端在随后的仲裁阶段中进行优先排序。