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公开(公告)号：US07073031B1
公开(公告)日：2006-07-04
申请号：US10740343
申请日：2003-12-18
IPC分类号： G06F12/00
CPC分类号： G06F9/52
摘要： A system for maintaining data coherency. The system includes a plurality of processors. A plurality of resources is also included. One portion of the resources is sharable with the plurality of processors and each one of the other ones of the resources being dedicated to a predetermined one of the processors. The system also includes a plurality of buffers. Each one of the buffers is associated with a corresponding one of the plurality of processors. Each one of the buffers is adapted to successively store information presented thereto in successive locations of such one of the buffers. The information includes requests from the corresponding one of the processor. The system includes a logic section responsive to each one of the requests provided by the plurality of processors. The logic section produces indicia indicating whether or not such one of the requests is a request for an operation with one of the sharable resources. The logic section inserts the indicia into a succeeding one of the locations of the buffers associated with such one of the processor providing such one of the requests. The logic section also simultaneously inserts such indicia into a next succeeding available location of the other ones of the plurality of buffers. The logic section inhibits execution of requests in the buffers stored in locations thereof succeeding the location having stored therein any such inserted indicia.
摘要翻译： 用于维护数据一致性的系统。 该系统包括多个处理器。 还包括多个资源。 资源的一部分与多个处理器共享，并且其中一个资源中的每一个专用于预定的一个处理器。 该系统还包括多个缓冲器。 每个缓冲器与多个处理器中的相应一个处理器相关联。 缓冲器中的每一个适于在这些缓冲器的连续位置中连续存储呈现给它的信息。 该信息包括来自相应处理器之一的请求。 该系统包括响应于由多个处理器提供的每个请求的逻辑部分。 逻辑部分产生指示这样的一个请求是否是具有可共享资源之一的操作的请求的标记。 逻辑部分将标记插入与提供这种请求之一的处理器之一相关联的缓冲器的后续位置之一。 逻辑部分还同时将这样的标记插入到多个缓冲器中的其他缓冲器的下一个后续可用位置。 逻辑部分禁止存储在其中存储有任何这样的插入标记的位置的位置中的缓冲器中的请求的执行。
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公开(公告)号：US07400672B1
公开(公告)日：2008-07-15
申请号：US10905393
申请日：2004-12-30
CPC分类号： H04L1/0045 , H04L2001/0094
摘要： A system for detecting transmission errors in a data transmission system includes a receiver for receiving a data packet transmitted thereto by a corresponding transmitter and transmitting the data packet to a destination device and an error detection device for receiving a plurality of protocol signals that control the operation of the transmitter and the receiver. The error detection device applies at least one predetermined rule to the protocol signals, wherein a violation of the at least one rule by the protocol signals indicates that an error in the transmission of the packet has occurred, and asserts an error signal when the at least one rule has been violated by the protocol signals. The system further includes a packet filtering device coupled to receive the error signal from the error detection device and the data packet from the receiver, wherein, upon receiving the asserted error signal, the packet filtering device terminates the transmission of the data packet to the destination device.
摘要翻译： 一种用于检测数据传输系统中的传输错误的系统，包括：接收机，用于接收由相应的发射机发射的数据分组，并将数据分组发送到目的设备;以及错误检测设备，用于接收控制该操作的多个协议信号 的发射机和接收机。 误差检测装置对协议信号应用至少一个预定规则，其中由协议信号违反至少一个规则指示已经发生了分组的传输中的错误，并且当至少发出了错误信号 一个规则被协议信号所违反。 该系统还包括一个分组过滤装置，它被耦合以从误差检测装置接收错误信号和从接收机接收数据分组，其中，在接收到断言的误差信号时，分组过滤装置终止数据分组到目的地的传输 设备。
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公开(公告)号：US08270322B1
公开(公告)日：2012-09-18
申请号：US10905391
申请日：2004-12-30
IPC分类号： H04J1/16
CPC分类号： G06F13/4217
摘要： A system for arbitrating a transmission of data includes a number K of transmitters, a request signal transmission device, a device valid signal transmission device, and a data valid logic device, wherein a transmitter asserts a request signal to request permission to begin a data transmission and transmits transmission-identifying information to a receiver. The data valid logic device deasserts a data valid signal based on the state of a wait signal, thereby preventing a transmission of data from each of the K transmitters at one clock cycle after a clock cycle at which the data signal is deasserted. An arbitration logic device of the receiver selects one of the number K of transmitters to grant permission to transmit data to the receiver and outputs an arbitration signal to a wait logic device instructing the wait logic device to deassert the wait signal of the selected trnasmitter.
摘要翻译： 用于仲裁数据传输的系统包括发射机数量K，请求信号传输设备，设备有效信号传输设备和数据有效逻辑设备，其中发射机断言请求信号以请求开始数据传输的许可 并将发送识别信息发送到接收机。 数据有效逻辑装置根据等待信号的状态取消数据有效信号，从而防止在数据信号被断言的时钟周期之后的一个时钟周期从每个K个发射机发送数据。 接收机的仲裁逻辑设备选择发射机数量K中的一个，以允许向接收机发送数据的许可，并将仲裁信号输出到等待逻辑装置，指示等待逻辑装置取消所选择的发射机的等待信号。
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公开(公告)号：US07337250B1
公开(公告)日：2008-02-26
申请号：US10905389
申请日：2004-12-30
IPC分类号： G06F13/42
CPC分类号： G06F13/4204
摘要： A method of transmitting data includes: A. receiving, at each of a plurality of data transmission devices of a transmitter, a data bit of a data word from a host; B. determining that a data word has been received from the host and asserting a data valid signal; C. transmitting the asserted data valid signal to a data valid register of a receiver including a plurality of data reception devices, each being coupled to a corresponding one of the plurality of data transmission devices of the transmitter; D. transmitting the data bit from each of the plurality of data transmission devices to the corresponding data reception device; E. inputting the data valid signal to each of the plurality of data reception devices to instruct the plurality of data reception devices to sample the data bit transmitted thereto from the corresponding data transmission device; wherein Step C occurs before Step D and Steps D and E occur substantially simultaneously.
摘要翻译： 一种发送数据的方法包括：A.在发送器的多个数据发送装置的每一个处，从主机接收数据字的数据位; B.确定已经从主机接收到数据字并断言数据有效信号; C.将所声明的数据有效信号发送到包括多个数据接收装置的接收机的数据有效寄存器，每个数据接收装置被耦合到发射机的多个数据传输装置中相应的一个; D.将数据位从多个数据传输设备中的每一个发送到相应的数据接收设备; E.向多个数据接收装置中的每个数据接收装置输入数据有效信号，指示多个数据接收装置对相应的数据发送装置发送的数据比特进行采样; 其中步骤C发生在步骤D之前，步骤D和E基本上同时发生。
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5.发明授权First-in/first-out (FIFO) information protection and error detection method and apparatus 有权先进先出（FIFO）信息保护和错误检测方法及装置公开(公告)号：US07383492B2
公开(公告)日：2008-06-03
申请号：US10392626
申请日：2003-03-20
申请人： Philip M. Sailer , Nicholas Paluzzi , Avinash Kallat , Stephen L. Scaringella , Krzysztof Dobecki
发明人： Philip M. Sailer , Nicholas Paluzzi , Avinash Kallat , Stephen L. Scaringella , Krzysztof Dobecki
CPC分类号： G06F11/1008 , H03M13/01 , H03M13/09
摘要： A system and method for determining data integrity as such data passes through a FIFO. A generator is provided for appending a bit in a predetermined bit location in each packet pushed into the FIFO in response clock signals. The appended bit is a function of the information pushed into the FIFO. A checker is provided for providing an indication of the information integrity in response to bits produced at an output of the FIFO in the predetermined bit location. In one embodiment, the generator is a parity generator and the checker is a parity checker. In one embodiment, during an initial test mode, one parity type is introduced into the FIFO by the parity generator and the opposite parity type is checked at the output of the FIFO by the parity checker to determine whether the parity checker is able to produce parity error signals. In another embodiment, the generator is a packet delimiter generator and the checker is a packet delimiter checker. In another embodiment, the generator is a frame delimiter generator and the checker is a frame delimiter checker.
摘要翻译： 用于当这些数据通过FIFO时确定数据完整性的系统和方法。 提供发生器用于在按照时钟信号被推入FIFO的每个分组中的一个预定比特位置中追加一位。 附加位是推送到FIFO中的信息的函数。 提供了一种检查器，用于响应于在预定比特位置中的FIFO的输出处产生的比特来提供信息完整性的指示。 在一个实施例中，发生器是奇偶校验发生器，并且检验器是奇偶校验器。 在一个实施例中，在初始测试模式期间，奇偶校验发生器将一个奇偶校验类型引入FIFO，并且在奇偶校验器的FIFO的输出处检查相反的奇偶校验类型，以确定奇偶检验器是否能够产生奇偶校验 错误信号。 在另一个实施例中，生成器是分组定界符生成器，并且检查器是分组定界符检查器。 在另一个实施例中，生成器是帧定界符生成器，并且检查器是帧分隔符检查器。
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6.发明授权System having plural processors and a uni-cast/broadcast communication arrangement 有权具有多个处理器和单播/广播通信装置的系统公开(公告)号：US06738842B1
公开(公告)日：2004-05-18
申请号：US09821484
申请日：2001-03-29
IPC分类号： G06F1516
CPC分类号： G06F15/177 , G06F3/0601 , G06F12/0866 , G06F2003/0692
摘要： A system having a plurality of processors, each one of the processors being adapted to issue a control signal and a processor ID code. Each one of the processors has: a unique, pre-assigned processor ID code, and a common software program. The software program operates to: receive the control signal and the processor ID code from the issuing one of the processors along with an indication of the one of the processors which issued the particular control signal and processor ID code; and test whether the received processor ID code is the same as the processor issuing the command and if so, generate one of the broadcast mode or uni-cast modes; otherwise, generate the other one of the broadcast or uni-cast modes.
摘要翻译： 一种具有多个处理器的系统，每个处理器适于发出控制信号和处理器ID代码。 每个处理器具有：独特的预分配处理器ID代码和通用软件程序。 软件程序用于：从发出的一个处理器接收控制信号和处理器ID代码以及发出特定控制信号和处理器ID代码的处理器之一的指示; 并测试接收到的处理器ID代码是否与发出命令的处理器相同，如果是，则生成广播模式或单播模式之一; 否则，生成另一个广播或单播模式。
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7.发明授权Address management for a shared memory region on a multi-processor controller board 有权多处理器控制器板上的共享内存区域的地址管理公开(公告)号：US06578128B1
公开(公告)日：2003-06-10
申请号：US09821493
申请日：2001-03-29
IPC分类号： G06F1210
CPC分类号： G06F12/0284 , G06F12/0866
摘要： A system having a memory with a plurality of contiguous processor memory regions and a plurality of processors. Each one of such processors is associated with a corresponding one of the processor memory regions. Each one of such processors provides a plurality of sets of successive processor addresses. The addresses in each one of such sets has a successive series of used addresses and a successive series of reserve addresses. The last used address in each one of the sets is separated from the first used address in the next successive set of addresses by a gap of addresses, G. A common address translator is fed by virtual addresses and maps the virtual addresses fed thereto to the memory addresses, such mapping being in accordance with the gap G to map each one of the sets of used processor addresses provided by each of the processors into the corresponding one of the contiguous processor memory regions.
摘要翻译： 一种具有具有多个连续处理器存储区域和多个处理器的存储器的系统。 这些处理器中的每一个与处理器存储器区域中的相应一个相关联。 这些处理器中的每一个提供多组连续的处理器地址。 这些集合中的每一个中的地址具有连续的一系列使用的地址和连续的一系列保留地址。 每一组中的最后一个使用的地址与下一个连续的地址集合中的第一个使用的地址与地址的间隙G分开。公共地址转换器由虚拟地址馈送，并将馈送到其的虚拟地址映射到 存储器地址，这样的映射根据间隙G将每个处理器提供的所使用的处理器地址集合中的每一个映射到相邻的处理器存储器区域中的一个。
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8.发明授权Storage controller with hardware emulation controller for emulation between control processor and transfer circuitry compatible to different processor 有权具有硬件仿真控制器的存储控制器，可在控制处理器和与不同处理器兼容的传输电路之间进行仿真公开(公告)号：US06560573B1
公开(公告)日：2003-05-06
申请号：US09365360
申请日：1999-07-30
IPC分类号： G06F1312
CPC分类号： G06F9/3879 , G06F11/261
摘要： A hardware emulation controller permits a high performance processor to be used with system circuitry that is configured for operation with a different processor. The hardware emulation controller is capable of modifying signals from the high performance processor for compatibility with the system circuitry. The hardware emulation controller is also capable of modifying signals from the system circuitry for compatibility with the high performance processor.
摘要翻译： 硬件仿真控制器允许将高性能处理器与配置为使用不同处理器进行操作的系统电路一起使用。 硬件仿真控制器能够修改来自高性能处理器的信号，以与系统电路兼容。 硬件仿真控制器还能够修改来自系统电路的信号，以与高性能处理器兼容。
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9.发明授权Computer storage system controller incorporating control store memory with primary and secondary data and parity areas 有权计算机存储系统控制器包含具有主要和次要数据和奇偶校验区域的控制存储存储器公开(公告)号：US06467047B1
公开(公告)日：2002-10-15
申请号：US09364931
申请日：1999-07-30
IPC分类号： G06F1110
CPC分类号： G06F11/1032
摘要： A computer storage system includes director boards which control transfer of data to and between a host computer, a system cache memory and a disk array. The directors are provided with features which enhance system performance and reliability. A hardware emulation controller permits a high performance processor to be used with existing system circuitry. A control store memory is organized with primary and secondary data areas and primary and secondary parity areas. Data is written to both the primary and secondary areas. A read request accesses data in the primary area and performs a retry in the secondary area in the event of a parity error. A power supply system includes on-board marginable power supplies to facilitate testing and power-up by-pass circuits for protection of sensitive circuitry. A system clock configuration employs primary and secondary clocks to ensure redundancy of synchronized timekeeping.
摘要翻译： 计算机存储系统包括控制数据传输到主计算机，系统高速缓冲存储器和磁盘阵列之间的导板。 董事会提供了增强系统性能和可靠性的功能。 硬件仿真控制器允许与现有系统电路一起使用高性能处理器。 控制存储器存储器具有主要和次要数据区域以及主要和次要奇偶校验区域。 数据被写入主区域和次区域。 读取请求访问主区域中的数据，并且在奇偶校验错误的情况下在辅助区域中执行重试。 电源系统包括板载可靠电源，以便于测试和上电旁路电路，以保护敏感电路。 系统时钟配置使用主时钟和辅助时钟来确保同步计时的冗余。
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公开(公告)号：US07099971B1
公开(公告)日：2006-08-29
申请号：US10606819
申请日：2003-06-26
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F13/1605
摘要： A system and method wherein a bus arbiter grants access to a bus to bus-coupled clients in order to provide access to a memory resource shared by the clients in response to “address retry” conditions induced by such clients. The bus arbiter provides access to the bus in response to whether one of the requesting clients experienced an “address retry” condition during its previous bus access. If such an address retry condition was experienced during its previous bus access, the bus arbiter grants such one of the requesting clients access to the bus at the earliest opportunity. Otherwise, the bus arbiter provides bus access to the requesting one, or ones, of the clients based on criteria independent of “address retry” conditions being induced on the bus.
摘要翻译： 一种系统和方法，其中总线仲裁器向总线耦合的客户端授予访问总线以便响应于由这些客户端引起的“地址重试”条件来提供对由客户端共享的存储器资源的访问。 总线仲裁器提供对总线的访问，以响应请求的客户端之一在其之前的总线访问期间是否经历了“地址重试”状态。 如果在其以前的总线访问期间遇到这样的地址重试条件，则总线仲裁器允许请求客户之一尽早访问总线。 否则，总线仲裁器基于独立于在总线上引起的“地址重试”条件的标准，向客户端的请求的一个或多个客户端提供总线访问。
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