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公开(公告)号：US07073031B1
公开(公告)日：2006-07-04
申请号：US10740343
申请日：2003-12-18
IPC分类号： G06F12/00
CPC分类号： G06F9/52
摘要： A system for maintaining data coherency. The system includes a plurality of processors. A plurality of resources is also included. One portion of the resources is sharable with the plurality of processors and each one of the other ones of the resources being dedicated to a predetermined one of the processors. The system also includes a plurality of buffers. Each one of the buffers is associated with a corresponding one of the plurality of processors. Each one of the buffers is adapted to successively store information presented thereto in successive locations of such one of the buffers. The information includes requests from the corresponding one of the processor. The system includes a logic section responsive to each one of the requests provided by the plurality of processors. The logic section produces indicia indicating whether or not such one of the requests is a request for an operation with one of the sharable resources. The logic section inserts the indicia into a succeeding one of the locations of the buffers associated with such one of the processor providing such one of the requests. The logic section also simultaneously inserts such indicia into a next succeeding available location of the other ones of the plurality of buffers. The logic section inhibits execution of requests in the buffers stored in locations thereof succeeding the location having stored therein any such inserted indicia.
摘要翻译： 用于维护数据一致性的系统。 该系统包括多个处理器。 还包括多个资源。 资源的一部分与多个处理器共享，并且其中一个资源中的每一个专用于预定的一个处理器。 该系统还包括多个缓冲器。 每个缓冲器与多个处理器中的相应一个处理器相关联。 缓冲器中的每一个适于在这些缓冲器的连续位置中连续存储呈现给它的信息。 该信息包括来自相应处理器之一的请求。 该系统包括响应于由多个处理器提供的每个请求的逻辑部分。 逻辑部分产生指示这样的一个请求是否是具有可共享资源之一的操作的请求的标记。 逻辑部分将标记插入与提供这种请求之一的处理器之一相关联的缓冲器的后续位置之一。 逻辑部分还同时将这样的标记插入到多个缓冲器中的其他缓冲器的下一个后续可用位置。 逻辑部分禁止存储在其中存储有任何这样的插入标记的位置的位置中的缓冲器中的请求的执行。
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公开(公告)号：US07400672B1
公开(公告)日：2008-07-15
申请号：US10905393
申请日：2004-12-30
CPC分类号： H04L1/0045 , H04L2001/0094
摘要： A system for detecting transmission errors in a data transmission system includes a receiver for receiving a data packet transmitted thereto by a corresponding transmitter and transmitting the data packet to a destination device and an error detection device for receiving a plurality of protocol signals that control the operation of the transmitter and the receiver. The error detection device applies at least one predetermined rule to the protocol signals, wherein a violation of the at least one rule by the protocol signals indicates that an error in the transmission of the packet has occurred, and asserts an error signal when the at least one rule has been violated by the protocol signals. The system further includes a packet filtering device coupled to receive the error signal from the error detection device and the data packet from the receiver, wherein, upon receiving the asserted error signal, the packet filtering device terminates the transmission of the data packet to the destination device.
摘要翻译： 一种用于检测数据传输系统中的传输错误的系统，包括：接收机，用于接收由相应的发射机发射的数据分组，并将数据分组发送到目的设备;以及错误检测设备，用于接收控制该操作的多个协议信号 的发射机和接收机。 误差检测装置对协议信号应用至少一个预定规则，其中由协议信号违反至少一个规则指示已经发生了分组的传输中的错误，并且当至少发出了错误信号 一个规则被协议信号所违反。 该系统还包括一个分组过滤装置，它被耦合以从误差检测装置接收错误信号和从接收机接收数据分组，其中，在接收到断言的误差信号时，分组过滤装置终止数据分组到目的地的传输 设备。
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公开(公告)号：US08270322B1
公开(公告)日：2012-09-18
申请号：US10905391
申请日：2004-12-30
IPC分类号： H04J1/16
CPC分类号： G06F13/4217
摘要： A system for arbitrating a transmission of data includes a number K of transmitters, a request signal transmission device, a device valid signal transmission device, and a data valid logic device, wherein a transmitter asserts a request signal to request permission to begin a data transmission and transmits transmission-identifying information to a receiver. The data valid logic device deasserts a data valid signal based on the state of a wait signal, thereby preventing a transmission of data from each of the K transmitters at one clock cycle after a clock cycle at which the data signal is deasserted. An arbitration logic device of the receiver selects one of the number K of transmitters to grant permission to transmit data to the receiver and outputs an arbitration signal to a wait logic device instructing the wait logic device to deassert the wait signal of the selected trnasmitter.
摘要翻译： 用于仲裁数据传输的系统包括发射机数量K，请求信号传输设备，设备有效信号传输设备和数据有效逻辑设备，其中发射机断言请求信号以请求开始数据传输的许可 并将发送识别信息发送到接收机。 数据有效逻辑装置根据等待信号的状态取消数据有效信号，从而防止在数据信号被断言的时钟周期之后的一个时钟周期从每个K个发射机发送数据。 接收机的仲裁逻辑设备选择发射机数量K中的一个，以允许向接收机发送数据的许可，并将仲裁信号输出到等待逻辑装置，指示等待逻辑装置取消所选择的发射机的等待信号。
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公开(公告)号：US07337250B1
公开(公告)日：2008-02-26
申请号：US10905389
申请日：2004-12-30
IPC分类号： G06F13/42
CPC分类号： G06F13/4204
摘要： A method of transmitting data includes: A. receiving, at each of a plurality of data transmission devices of a transmitter, a data bit of a data word from a host; B. determining that a data word has been received from the host and asserting a data valid signal; C. transmitting the asserted data valid signal to a data valid register of a receiver including a plurality of data reception devices, each being coupled to a corresponding one of the plurality of data transmission devices of the transmitter; D. transmitting the data bit from each of the plurality of data transmission devices to the corresponding data reception device; E. inputting the data valid signal to each of the plurality of data reception devices to instruct the plurality of data reception devices to sample the data bit transmitted thereto from the corresponding data transmission device; wherein Step C occurs before Step D and Steps D and E occur substantially simultaneously.
摘要翻译： 一种发送数据的方法包括：A.在发送器的多个数据发送装置的每一个处，从主机接收数据字的数据位; B.确定已经从主机接收到数据字并断言数据有效信号; C.将所声明的数据有效信号发送到包括多个数据接收装置的接收机的数据有效寄存器，每个数据接收装置被耦合到发射机的多个数据传输装置中相应的一个; D.将数据位从多个数据传输设备中的每一个发送到相应的数据接收设备; E.向多个数据接收装置中的每个数据接收装置输入数据有效信号，指示多个数据接收装置对相应的数据发送装置发送的数据比特进行采样; 其中步骤C发生在步骤D之前，步骤D和E基本上同时发生。
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公开(公告)号：US07254654B1
公开(公告)日：2007-08-07
申请号：US10813989
申请日：2004-04-01
IPC分类号： G06F3/00
CPC分类号： G06F3/0656 , G06F3/0613 , G06F3/0676
摘要： A data transfer device is disclosed for writing data to and reading data from a disk drive system through a plurality of ports of the data transfer device. The data transfer device includes a first buffer for serially receiving, from a host system, control portions of data read requests and data write transfers; a second buffer for serially receiving, from the host system, data portions of data write transfers received by the first buffer; and N temporary storage devices, wherein N is a positive integer, coupled to the first buffer and the second buffer, the N temporary storage devices for parallelly receiving and temporarily storing consecutive control portions of the data read transfers and data write transfers from the first buffer. Up to N of the data read transfers and data write transfers are transferred to the disk drive system through the plurality of ports simultaneously.
摘要翻译： 公开了一种数据传输装置，用于通过数据传送装置的多个端口将数据写入和读取来自磁盘驱动器系统的数据。 数据传送装置包括：第一缓冲器，用于从主机系统串行地接收数据读取请求和数据写入传送的控制部分; 用于从所述主机系统串行地接收由所述第一缓冲器接收的数据写入传输的数据部分的第二缓冲器; N个临时存储装置，其中N是正整数，耦合到第一缓冲器和第二缓冲器，N个临时存储装置用于并行地接收和临时存储来自第一缓冲器的数据读取传送和数据写入传输的连续控制部分 。 最多N个数据读取传输和数据写入传输通过多个端口同时传输到磁盘驱动器系统。
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公开(公告)号：US07987229B1
公开(公告)日：2011-07-26
申请号：US11769744
申请日：2007-06-28
申请人： Jeffrey Kinne , John O'Shea , Michael Sgrosso , William F. Baxter, III , Christopher S. MacLellan
发明人： Jeffrey Kinne , John O'Shea , Michael Sgrosso , William F. Baxter, III , Christopher S. MacLellan
CPC分类号： G06F13/385 , G06F3/0658 , G06F13/28 , H04L67/1097
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE端点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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公开(公告)号：US07631128B1
公开(公告)日：2009-12-08
申请号：US11769747
申请日：2007-06-28
申请人： Michael Sgrosso , William F. Baxter, III , Jeffrey Kinne , Christopher S. MacLellan , John O'Shea
发明人： Michael Sgrosso , William F. Baxter, III , Jeffrey Kinne , Christopher S. MacLellan , John O'Shea
CPC分类号： G06F13/387 , G06F3/06 , G06F2213/0026 , H04L12/56
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE端点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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公开(公告)号：US07272668B1
公开(公告)日：2007-09-18
申请号：US10606872
申请日：2003-06-26
申请人： John K. Walton , Ofer Porat , Christopher S. MacLellan , Daniel Castel , Kendell A. Chilton , Brian K. Campbell , Gregory S. Robidoux , Brian D. Magnuson
发明人： John K. Walton , Ofer Porat , Christopher S. MacLellan , Daniel Castel , Kendell A. Chilton , Brian K. Campbell , Gregory S. Robidoux , Brian D. Magnuson
CPC分类号： G06F1/181 , G06F1/184 , G06F1/185 , G06F1/186 , G06F3/0601 , G06F2003/0692
摘要： A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.
摘要翻译： 具有多个印刷电路的系统具有在其上具有电气部件的每个印刷电路。 背板携带指示插入到该背板中的多个印刷电路板上的电气部件的性能特征的信号。 性能特征可以是例如组件速度，操作协议等。在检测到这种不兼容性时，系统启动被中断。 在启动之后，当插入其上具有电气部件的附加印刷电路，其操作与多个印刷电路板上的电气部件不兼容的操作进入背板时，这种附加印刷电路上的电气部件将不会电耦合到 电子部件在多个印刷电路板的电气部件上的附加印刷电路板上。
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公开(公告)号：US06993705B1
公开(公告)日：2006-01-31
申请号：US09746174
申请日：2000-12-21
IPC分类号： G06F11/00
CPC分类号： H03M13/091 , G11B20/1833 , H03M13/09
摘要： A method for determining Cyclic Redundancy Check (CRC) parity of data, such data comprising a plurality of bytes, each one of the bytes having a parity bit, the plurality of bytes of data having a CRC. The method includes generating the parity of the parity bits of the plurality of bytes of the data, such generated parity being the parity of the CRC of such data. The method includes: generating parity of the parity bits of the plurality of data bytes; and comparing such generated parity with the parity bit of the CRC of the data. The method receives data having a plurality of N bytes: [D(0), D(1), . . . , D(N−1]) each byte having a parity bit p and computes the parity of [P(0), P(1), . . . P(N−1)].
摘要翻译： 一种用于确定数据的循环冗余校验（CRC）奇偶校验的方法，所述数据包括多个字节，每个字节具有奇偶校验位，所述多个字节的数据具有CRC。 该方法包括产生数据的多个字节的奇偶校验位的奇偶校验，所产生的奇偶校验是这种数据的CRC的奇偶校验。 该方法包括：产生多个数据字节的奇偶校验位的奇偶校验; 并将该生成的奇偶校验与数据的CRC的奇偶校验位进行比较。 该方法接收具有多个N字节的数据：[D（0），D（1）]。 。 。 ，D（N-1））每个字节具有奇偶校验位p并计算[P（0），P（1）]的奇偶校验。 。 。 P（N-1）]。
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10.发明授权Data storage system adapted to validate error detection logic used in such system 有权数据存储系统适用于验证在这种系统中使用的错误检测逻辑公开(公告)号：US06886116B1
公开(公告)日：2005-04-26
申请号：US09915854
申请日：2001-07-26
IPC分类号： G06F11/00 , G06F11/267
CPC分类号： G06F11/2215
摘要： A system for validating error detection logic in a system. The system includes a plurality of information paths, each one of such paths having associated therewith an error detection logic, each one of the paths having a plurality of information bits. A test word buffer is provided for receiving a test word, such test word indicating a particular one of the plurality of information bits in a particular one of the information paths to be corrupted. The system includes a plurality of fault injectors responsive to the test word received by the buffer. Each one of the fault injectors is disposed in a corresponding one of the information paths prior to the associated the error detection logic. Each one of such fault injectors corrupts a selected one of the information bits in the corresponding one of the information paths in response to the test word received by the buffer to test whether the associated error detection logic detects such injected fault. The test word buffer stores an indication as to whether software is one of the directors is to be tested for response to a detected fault.
摘要翻译： 用于验证系统中的错误检测逻辑的系统。 该系统包括多个信息路径，这些路径中的每一个具有与其相关联的错误检测逻辑，每个路径具有多个信息位。 提供测试字缓冲器用于接收测试字，所述测试字指示要被损坏的特定信息路径中的多个信息位中的特定一个。 该系统包括响应于由缓冲器接收的测试字的多个故障注入器。 故障注入器中的每一个在相关联的错误检测逻辑之前被布置在相应的信息路径之一中。 每个这样的故障注入器响应于由缓冲器接收到的测试字来破坏对应的一个信息路径中的选定的一个信息比特，以测试相关联的错误检测逻辑是否检测到这种注入的故障。 测试字缓冲器存储关于软件是否是导向器之一被测试以响应于检测到的故障的指示。
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