公开(公告)号：US07073031B1

公开(公告)日：2006-07-04

申请号：US10740343

申请日：2003-12-18

申请人： Christopher S. MacLellan ,  Avinash Kallat ,  Almir Davis ,  Stephen L. Scaringella

发明人： Christopher S. MacLellan ,  Avinash Kallat ,  Almir Davis ,  Stephen L. Scaringella

IPC分类号： G06F12/00

CPC分类号： G06F9/52

摘要： A system for maintaining data coherency. The system includes a plurality of processors. A plurality of resources is also included. One portion of the resources is sharable with the plurality of processors and each one of the other ones of the resources being dedicated to a predetermined one of the processors. The system also includes a plurality of buffers. Each one of the buffers is associated with a corresponding one of the plurality of processors. Each one of the buffers is adapted to successively store information presented thereto in successive locations of such one of the buffers. The information includes requests from the corresponding one of the processor. The system includes a logic section responsive to each one of the requests provided by the plurality of processors. The logic section produces indicia indicating whether or not such one of the requests is a request for an operation with one of the sharable resources. The logic section inserts the indicia into a succeeding one of the locations of the buffers associated with such one of the processor providing such one of the requests. The logic section also simultaneously inserts such indicia into a next succeeding available location of the other ones of the plurality of buffers. The logic section inhibits execution of requests in the buffers stored in locations thereof succeeding the location having stored therein any such inserted indicia.

摘要翻译： 用于维护数据一致性的系统。 该系统包括多个处理器。 还包括多个资源。 资源的一部分与多个处理器共享，并且其中一个资源中的每一个专用于预定的一个处理器。 该系统还包括多个缓冲器。 每个缓冲器与多个处理器中的相应一个处理器相关联。 缓冲器中的每一个适于在这些缓冲器的连续位置中连续存储呈现给它的信息。 该信息包括来自相应处理器之一的请求。 该系统包括响应于由多个处理器提供的每个请求的逻辑部分。 逻辑部分产生指示这样的一个请求是否是具有可共享资源之一的操作的请求的标记。 逻辑部分将标记插入与提供这种请求之一的处理器之一相关联的缓冲器的后续位置之一。 逻辑部分还同时将这样的标记插入到多个缓冲器中的其他缓冲器的下一个后续可用位置。 逻辑部分禁止存储在其中存储有任何这样的插入标记的位置的位置中的缓冲器中的请求的执行。

公开(公告)号：US07383492B2

公开(公告)日：2008-06-03

申请号：US10392626

申请日：2003-03-20

申请人： Philip M. Sailer ,  Nicholas Paluzzi ,  Avinash Kallat ,  Stephen L. Scaringella ,  Krzysztof Dobecki

发明人： Philip M. Sailer ,  Nicholas Paluzzi ,  Avinash Kallat ,  Stephen L. Scaringella ,  Krzysztof Dobecki

IPC分类号： G06F11/00 ,  H03M13/00 ,  G11C29/00

CPC分类号： G06F11/1008 ,  H03M13/01 ,  H03M13/09

摘要： A system and method for determining data integrity as such data passes through a FIFO. A generator is provided for appending a bit in a predetermined bit location in each packet pushed into the FIFO in response clock signals. The appended bit is a function of the information pushed into the FIFO. A checker is provided for providing an indication of the information integrity in response to bits produced at an output of the FIFO in the predetermined bit location. In one embodiment, the generator is a parity generator and the checker is a parity checker. In one embodiment, during an initial test mode, one parity type is introduced into the FIFO by the parity generator and the opposite parity type is checked at the output of the FIFO by the parity checker to determine whether the parity checker is able to produce parity error signals. In another embodiment, the generator is a packet delimiter generator and the checker is a packet delimiter checker. In another embodiment, the generator is a frame delimiter generator and the checker is a frame delimiter checker.

摘要翻译： 用于当这些数据通过FIFO时确定数据完整性的系统和方法。 提供发生器用于在按照时钟信号被推入FIFO的每个分组中的一个预定比特位置中追加一位。 附加位是推送到FIFO中的信息的函数。 提供了一种检查器，用于响应于在预定比特位置中的FIFO的输出处产生的比特来提供信息完整性的指示。 在一个实施例中，发生器是奇偶校验发生器，并且检验器是奇偶校验器。 在一个实施例中，在初始测试模式期间，奇偶校验发生器将一个奇偶校验类型引入FIFO，并且在奇偶校验器的FIFO的输出处检查相反的奇偶校验类型，以确定奇偶检验器是否能够产生奇偶校验 错误信号。 在另一个实施例中，生成器是分组定界符生成器，​​并且检查器是分组定界符检查器。 在另一个实施例中，生成器是帧定界符生成器，​​并且检查器是帧分隔符检查器。

公开(公告)号：US08356124B1

公开(公告)日：2013-01-15

申请号：US10846386

申请日：2004-05-14

申请人： Almir Davis ,  Michael Sgrosso ,  William F. Baxter, III ,  Avinash Kallat

发明人： Almir Davis ,  Michael Sgrosso ,  William F. Baxter, III ,  Avinash Kallat

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F13/368 ,  G06F13/14 ,  H04L12/40

CPC分类号： G06F13/362

摘要： A data transfer system includes a PCI Express transaction layer having an input for serially receiving posted and non-posted request packets and completion packets; an application layer coupled to the PCI Express transaction layer for receiving posted and non-posted request packets and completion packets from the PCI Express transaction layer; a first transmission interface coupling the application layer to the PCI Express transaction layer; and a second transmission interface coupling the application layer to the PCI Express transaction layer. The PCI Express transaction layer transmits posted and non-posted request packets to the application layer over the first transmission interface and transmits completion packets to the application layer over the second transmission interface.

摘要翻译： 数据传输系统包括具有用于串行接收发布和未发布的请求分组和完成分组的输入的PCI Express事务层; 耦合到PCI Express事务层的应用层，用于从PCI Express事务层接收发布和未发布的请求分组和完成分组; 将应用层耦合到PCI Express事务层的第一传输接口; 以及将应用层耦合到PCI Express事务层的第二传输接口。 PCI Express事务层通过第一传输接口将发布和未发布的请求数据包发送到应用层，并通过第二个传输接口将完成数据包发送到应用层。

公开(公告)号：US07162559B1

公开(公告)日：2007-01-09

申请号：US11076618

申请日：2005-03-08

申请人： Avinash Kallat ,  John Phinney ,  Amnon Izhar

发明人： Avinash Kallat ,  John Phinney ,  Amnon Izhar

IPC分类号： G06F13/14

CPC分类号： G06F13/24

摘要： An interrupt controller enables multiple CPUs to control access to an increased number of interrupts. Each of a plurality of CPUs is able to block interrupts written to the interrupt controller at multiple levels. First, each CPU is able to block interrupts at the interrupt level. In other words, a CPU is able to block one or more individual interrupt requests from I/O devices from being sent to that CPU. Second, each CPU is able to block interrupts from one or more entire MSI interrupt registers from being sent to that CPU. The interrupt controller is fully programmable by the CPUs in software and thus is very flexible, as the priority of interrupts can be controlled by the CPUs according to the requirements of the CPUs based on the various operational demands of the CPUs. Any of 512 possible interrupt requests are capable of being routed to any particular one CPU, any combination of the CPUs or to all of the CPUs.

摘要翻译： 中断控制器允许多个CPU控制对更多数量中断的访问。 多个CPU中的每一个能够阻止以多个级别写入中断控制器的中断。 首先，每个CPU都能够在中断级别阻止中断。 换句话说，CPU能够阻止来自I / O设备的一个或多个单独的中断请求被发送到该CPU。 其次，每个CPU都能够阻止来自一个或多个整个MSI中断寄存器的中断发送到该CPU。 中断控制器可以由CPU以软件完全编程，因此非常灵活，因为中断的优先级可以由CPU根据CPU的各种操作需求根据CPU的要求进行控制。 任何512个可能的中断请求能够被路由到任何特定的一个CPU，CPU或所有CPU的任何组合。

公开(公告)号：US08478951B1

公开(公告)日：2013-07-02

申请号：US13447048

申请日：2012-04-13

申请人： Michael W. Healey ,  J. Michael Dunbar ,  Avinash Kallat ,  Michael Craig Fishman

发明人： Michael W. Healey ,  J. Michael Dunbar ,  Avinash Kallat ,  Michael Craig Fishman

IPC分类号： G06F12/16

CPC分类号： G06F11/1453 ,  G06F2201/83

摘要： Techniques for performing de-duplication for data blocks in a computer storage environment. At least one chunking/hashing unit receives input data from a source and processes it to output data blocks and content addresses for them. In one aspect, the chunking/hashing unit outputs all blocks without checking to see whether any is a duplicate of a block previously stored on the storage environment. In another aspect, each data block is processed by one of a plurality of distributed object addressable storage (OAS) devices that each is selected to process data blocks having content addresses with a particular range. The OAS devices determine whether each received to data block is a duplicate of another previously stored on the computer storage environment, and when it is not, stores the data block.

摘要翻译： 在计算机存储环境中执行数据块重复数据删除的技术。 至少一个分组/散列单元从源接收输入数据并处理它以输出数据块和它们的内容地址。 在一个方面，分块/散列单元输出所有块而不检查以查看先前存储在存储环境中的块是否是重复的。 在另一方面，每个数据块由多个分布式对象可寻址存储（OAS）设备中的一个处理，每个分配对象可寻址存储（OAS）设备被选择以处理具有特定范围的内容地址的数据块。 OAS设备确定接收到数据块的每个是否与以前存储在计算机存储环境中的另一个重复，并且当不是时，存储数据块。

公开(公告)号：US06584513B1

公开(公告)日：2003-06-24

申请号：US09540827

申请日：2000-03-31

申请人： Avinash Kallat ,  Robert Thibault

发明人： Avinash Kallat ,  Robert Thibault

IPC分类号： G06F1300

CPC分类号： G06F13/28

摘要： A direct memory access (DMA) transmitter includes: (a) a data register; and (b) a transmitter state machine. Requested data at an address provided by a source is read from the random access memory then transferred for storage in the data register. The central processing unit also sends a control signal to the transmit state machine. The control signal indicates to the transmit state machine whether the read data is a most recent copy of the requested data in random access memory or whether the most recent copy of the requested data is still resident in the local cache memory. In response to the control signal, if the most recent data is in the local cache memory, the transmit state machine inhibits the data that was read from random access memory and now stored in data register from passing to the transmitter output. Transmit state machine then performs a second data transfer request at the same address, the second requested data being transferred from the local cache memory to the random access memory. The transmit state machine reads the second requested data from the random access memory. The second requested data is the most recent data available in the random access memory. The transmit state machine then stores such second requested data into the data register, such stored second requested data then being transferred to the transmitter output.

摘要翻译： 直接存储器访问（DMA）发送器包括：（a）数据寄存器; 和（b）发射机状态机。 从源提供的地址处的请求的数据从随机存取存储器中读取，然后传送以存储在数据寄存器中。 中央处理单元还向发送状态机发送控制信号。 控制信号向发送状态机指示读取数据是随机存取存储器中所请求数据的最新副本，还是所请求数据的最新副本是否仍驻留在本地高速缓冲存储器中。 响应于控制信号，如果最近的数据在本地高速缓冲存储器中，则发送状态机禁止从随机存取存储器读取的数据，并且现在存储在数据寄存器中，从而传递到发送器输出。 然后，发送状态机在相同地址执行第二数据传输请求，第二请求数据从本地高速缓冲存储器传送到随机存取存储器。 发送状态机从随机存取存储器读取第二请求数据。 第二个请求的数据是随机存取存储器中可用的最新数据。 然后，发送状态机将这样的第二请求数据存储到数据寄存器中，这样存储的第二请求数据然后被传送到发送器输出。

公开(公告)号：US08200923B1

公开(公告)日：2012-06-12

申请号：US12347447

申请日：2008-12-31

申请人： Michael W. Healey ,  J. Michael Dunbar ,  Avinash Kallat ,  Michael Craig Fishman

发明人： Michael W. Healey ,  J. Michael Dunbar ,  Avinash Kallat ,  Michael Craig Fishman

IPC分类号： G06F12/16

CPC分类号： G06F11/1453 ,  G06F2201/83

摘要： Techniques for performing de-duplication for data blocks in a computer storage environment. At least one chunking/hashing unit receives input data from a source and processes it to output data blocks and content addresses for them. In one aspect, the chunking/hashing unit outputs all blocks without checking to see whether any is a duplicate of a block previously stored on the storage environment. In another aspect, each data block is processed by one of a plurality of distributed object addressable storage (OAS) devices that each is selected to process data blocks having content addresses with a particular range. The OAS devices determine whether each received data block is a duplicate of another previously stored on the computer storage environment, and when it is not, stores the data block.

摘要翻译： 在计算机存储环境中执行数据块重复数据删除的技术。 至少一个分组/散列单元从源接收输入数据并处理它以输出数据块和它们的内容地址。 在一个方面，分块/散列单元输出所有块而不检查以查看先前存储在存储环境中的块是否是重复的。 在另一方面，每个数据块由多个分布式对象可寻址存储（OAS）设备中的一个处理，每个分配对象可寻址存储（OAS）设备被选择以处理具有特定范围的内容地址的数据块。 OAS设备确定每个接收的数据块是否与先前存储在计算机存储环境中的另一个数据块重复，并且如果不是，则存储数据块。

公开(公告)号：US07328296B1

公开(公告)日：2008-02-05

申请号：US11324695

申请日：2006-01-03

申请人： Naser Marmash ,  Avinash Kallat ,  Brandon L. Paul ,  Mark Botello ,  Andrew Kniager

发明人： Naser Marmash ,  Avinash Kallat ,  Brandon L. Paul ,  Mark Botello ,  Andrew Kniager

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

摘要翻译： 一种具有中断保持寄存器的中断处理系统，每个中断处理系统对应于不同类别的中断。 写入队列中断保存寄存器所需的服务。 中断向量寄存器具有对应于不同类别中断的位位置。 读取队列具有耦合到多个中断保持寄存器和中断向量寄存器的输入。 检测逻辑耦合在由写入和读取队列馈送的仲裁器之间，以及处理器，用于：（a）指示中断何时从写入仲裁器传递到处理器; （b）检测这种传递中断的中断类; （c）使能与中断向量寄存器中检测到的中断类别相对应的位位置之一存储指示这种检测到的中断类别的服务要求的状态; 和（d）其中存储在中断向量寄存器中的数据通过读队列和仲裁器选择器传递给处理器。

公开(公告)号：US06609164B1

公开(公告)日：2003-08-19

申请号：US09680157

申请日：2000-10-05

申请人： Avinash Kallat

发明人： Avinash Kallat

IPC分类号： G06F1328

CPC分类号： G06F13/28

摘要： A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives. The method includes transferring messages through a messaging network with the data being transferred between the host computer/server and the bank of disk drives through a cache memory, such message network being independent of the cache memory.

摘要翻译： 系统接口包括多个第一导向器，多个第二导向器，数据传输部分和消息网络。 数据传送部分包括高速缓冲存储器。 高速缓存存储器耦合到多个第一和第二导向器。 消息传递网络独立于数据传送部分运行，并且这样的网络耦合到多个第一董事和多个第二董事。 第一和第二位董事通过消息传递网络响应第一任董事和第二任董事之间的信息，控制第一任董事与第二任董事之间的数据转移，以促进第一任董事与第二任董事之间的数据转移。 数据通过数据传输部分的高速缓冲存储器。 一种用于操作适于在主计算机/服务器和一组磁盘驱动器之间传送数据的数据存储系统的方法。 该方法包括通过消息传递网络传送消息，数据通过高速缓冲存储器在主机计算机/服务器和磁盘驱动器组之间传输，这样的消息网络独立于高速缓冲存储器。

公开(公告)号：US07818447B1

公开(公告)日：2010-10-19

申请号：US10402009

申请日：2003-03-28

申请人： Brett D. Niver ,  Steven R. Chalmer ,  Steven T. McClure ,  Stephen D. MacArthur ,  Avinash Kallat

发明人： Brett D. Niver ,  Steven R. Chalmer ,  Steven T. McClure ,  Stephen D. MacArthur ,  Avinash Kallat

IPC分类号： G06F15/16

CPC分类号： G06F15/17368

摘要： Described is an end-to-end broadcast-based messaging technique used in controlling message flow in a data storage system. Each node stores flow control state information about all the nodes which is used in determining whether to send a data transmission to a receiving node. The flow control state information includes an indicator as to whether each node is receiving incoming data transmissions. If a node is not receiving incoming data transmissions, the flow control state information also includes an associated expiration time. Data transmissions are resumed to a receiving node based on the earlier of a sending node determining that the expiration time has lapsed, or receiving a control message from the receiving node explicitly turning on data transmissions. Each node maintains and updates its local copy of the flow control state information in accordance with control messages sent by each node to turn on and off data transmissions. Each node sends out control messages in accordance with predetermined threshold levels taking into account hardware and/or software resources for message buffering.

摘要翻译： 描述了一种用于控制数据存储系统中的消息流的端对端基于广播的消息收发技术。 每个节点存储关于用于确定是否向接收节点发送数据传输的所有节点的流控制状态信息。 流控制状态信息包括关于每个节点是否正在接收输入数据传输的指示符。 如果节点没有接收传入数据传输，则流控制状态信息还包括相关联的到期时间。 基于发送节点的早期确定过期时间已经过去或者从接收节点明确地接收数据传输接收控制消息，数据传输被恢复到接收节点。 每个节点根据每个节点发送的控制消息来维护和更新其流控制状态信息的本地副本，以打开和关闭数据传输。 每个节点考虑到用于消息缓冲的硬件和/或软件资源，根据预定的阈值级别发出控制消息。