公开(公告)号：US5384279A

公开(公告)日：1995-01-24

申请号：US144091

申请日：1993-10-27

申请人： Andre Stolmeijer ,  Paulus M. T. M. Van Attekum ,  Hubertus Den Blanken ,  Paulus A. Van Der Plas ,  Reinier De Werdt

发明人： Andre Stolmeijer ,  Paulus M. T. M. Van Attekum ,  Hubertus Den Blanken ,  Paulus A. Van Der Plas ,  Reinier De Werdt

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/70

CPC分类号： H01L21/823807 ,  H01L21/2652 ,  H01L27/0928 ,  Y10S438/919

摘要： A method of manufacturing a semiconductor device is set forth, comprising a silicon body (1) having a surface (4) where there are situated a number of semiconductor regions (5, 6) and field oxide regions (7). The semiconductor regions is formed, after the field oxide regions have been provided, by implantations of n-type and p-type dopants. In accordance with the invention the implantations with the n-type dopant (10, 11, 14), which are performed using an implantation mask (8) provided on the surface and comprising openings (9) at the area of a part of the semiconductor regions (5) to be formed, are combined with the implantations with the p-type dopant (12, 13, 15) which are carried out without using the implantation mask. Thus, the semiconductor regions (5, 6) are realised by means of a single implantation mask (8).

摘要翻译： 提出了一种制造半导体器件的方法，包括具有表面（4）的硅体（1），其中位于多个半导体区域（5,6）和场氧化物区域（7）的表面（4）。 在提供场氧化物区域之后，通过n型和p型掺杂剂的注入形成半导体区域。 根据本发明，使用设置在表面上的注入掩模（8）进行n型掺杂剂（10,11,14）的注入，并且在半导体的一部分区域包括开口（9） 要形成的区域（5）与不使用注入掩模执行的p型掺杂剂（12,13,15）的注入组合。 因此，通过单个注入掩模（8）实现半导体区域（5,6）。

公开(公告)号：US5015602A

公开(公告)日：1991-05-14

申请号：US522490

申请日：1990-05-10

申请人： Paulus A. Van Der Plas ,  Reinier De Werdt

发明人： Paulus A. Van Der Plas ,  Reinier De Werdt

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/762

CPC分类号： H01L21/76229

摘要： A method of manufacturing a semiconductor device, in which a depression (1,2,3) in a surface (4) of a semiconductor substrate (5) is filled by covering it with a preplanarized filling layer (8,19,22) and a further planarization layer (9), after which the substrate (5) is brought into contact with an etchant, in which both layers (8,19,22) and (9) are etched at substantially the same rate. According to the invention, the preplanarized filling layer (8,19,22) is formed by covering the surface (4) with a layer of filling material (6) and then removing it beside the depression (1,2,3) over part of its thickness. Thus, the depression (1,2,3) is filled homogeneously in a comparatively simple manner with material of the filling layer (6).

摘要翻译： 一种制造半导体器件的方法，其中半导体衬底（5）的表面（4）中的凹陷（1,2,3）通过用预共面填充层（8,19,22）覆盖而被填充，并且 另外的平坦化层（9），然后使衬底（5）与蚀刻剂接触，其中两个层（8,19,22）和（9）以基本上相同的速率被蚀刻。 根据本发明，通过用一层填充材料（6）覆盖表面（4），然后在凹部（1,2,3）上方部分地将其去除，形成预平面化填充层（8,19,22） 的厚度。 因此，用填充层（6）的材料以相对简单的方式均匀地填充凹陷（1,2,3）。

公开(公告)号：US5254494A

公开(公告)日：1993-10-19

申请号：US896082

申请日：1992-06-08

申请人： Paulus A. Van Der Plas ,  Nicole A. H. F. Wils ,  Andreas H. Montree

发明人： Paulus A. Van Der Plas ,  Nicole A. H. F. Wils ,  Andreas H. Montree

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/32 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/28211 ,  H01L21/32 ,  H01L21/76202 ,  Y10S148/117

摘要： A method of manufacturing a semiconductor device includes forming field oxide regions (17) in a surface (1) of a silicon body (2) through oxidation, which body is provided with an oxidation mask (15) formed in a layered structure provided on the surface with a lower layer (4) of silicon oxide, an intermediate layer (5) of polycrystalline silicon and an upper layer (6) of a material including silicon nitride in which windows (8) are etched into the upper layer. The intermediate layer is etched away inside the windows and below an edge (10) of the windows, a cavity (11) is formed below the edge, and a material including silicon nitride is provided in the cavity. The material including silicon nitride is provided in the cavity while the surface of the silicon body situated inside the windows is still covered by a layer of silicon oxide, preferably with the lower layer of the layered structure. Field oxide regions can be provided in this way having the same dimensions as the photoresist mask (7) used for etching the window into the upper layer, while in addition a gate oxide (22) free from defects can be provided on the active regions (21) of the silicon body situated between the field oxide regions.

公开(公告)号：US5316966A

公开(公告)日：1994-05-31

申请号：US101797

申请日：1993-08-03

申请人： Paulus A. Van Der Plas ,  Herbert Lifka ,  Robertus D. J. Verhaar

发明人： Paulus A. Van Der Plas ,  Herbert Lifka ,  Robertus D. J. Verhaar

IPC分类号： G03F1/08 ,  H01L21/027 ,  H01L21/30 ,  H01L21/32 ,  H01L21/68 ,  H01L23/544 ,  H01L21/302

CPC分类号： H01L23/544 ,  H01L21/32 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S148/102

摘要： A method of manufacturing mask alignment marks on an active surface of a semiconductor substrate (12) is disclosed, in which first, at least one layer (13) of a material resistant to oxidation is formed on the active surface, after which by a local etching of this layer, zones (15') for isolation by a field oxide, are defined simultaneously with the alignment marks (17'). There are formed, after the local etching of the layer (13) of anti-oxidation material while using the remaining parts of the anti-oxidation layer as a mask, depressions (26) at the substrate surface of a given depth at least at locations containing the alignment marks, which locations are designated as alignment windows (18) and the surface of the substrate is then exposed within the windows, and finally a thermal oxidation step is effected to obtain the field oxide (19'), during which the alignment marks (18) are simultaneously covered by oxide (24).

摘要翻译： 公开了一种在半导体衬底（12）的有源表面上制造掩模对准标记的方法，其中首先，在活性表面上形成至少一层耐氧化材料层（13），然后通过局部 该层的蚀刻与场氧化物隔离的区域（15'）与对准标记（17'）同时定义。 在使用抗氧化层的其余部分作为掩模的同时，在局部蚀刻抗氧化材料层（13）之后，形成至少在位置处的给定深度的基板表面处的凹陷（26） 包含对准标记，这些位置被指定为对齐窗口（18），然后在窗口内露出基板的表面，最后进行热氧化步骤以获得场氧化物（19'），在此期间对准 标记（18）同时被氧化物（24）覆盖。