公开(公告)号：US5316966A

公开(公告)日：1994-05-31

申请号：US101797

申请日：1993-08-03

申请人： Paulus A. Van Der Plas ,  Herbert Lifka ,  Robertus D. J. Verhaar

发明人： Paulus A. Van Der Plas ,  Herbert Lifka ,  Robertus D. J. Verhaar

IPC分类号： G03F1/08 ,  H01L21/027 ,  H01L21/30 ,  H01L21/32 ,  H01L21/68 ,  H01L23/544 ,  H01L21/302

CPC分类号： H01L23/544 ,  H01L21/32 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S148/102

摘要： A method of manufacturing mask alignment marks on an active surface of a semiconductor substrate (12) is disclosed, in which first, at least one layer (13) of a material resistant to oxidation is formed on the active surface, after which by a local etching of this layer, zones (15') for isolation by a field oxide, are defined simultaneously with the alignment marks (17'). There are formed, after the local etching of the layer (13) of anti-oxidation material while using the remaining parts of the anti-oxidation layer as a mask, depressions (26) at the substrate surface of a given depth at least at locations containing the alignment marks, which locations are designated as alignment windows (18) and the surface of the substrate is then exposed within the windows, and finally a thermal oxidation step is effected to obtain the field oxide (19'), during which the alignment marks (18) are simultaneously covered by oxide (24).

摘要翻译： 公开了一种在半导体衬底（12）的有源表面上制造掩模对准标记的方法，其中首先，在活性表面上形成至少一层耐氧化材料层（13），然后通过局部 该层的蚀刻与场氧化物隔离的区域（15'）与对准标记（17'）同时定义。 在使用抗氧化层的其余部分作为掩模的同时，在局部蚀刻抗氧化材料层（13）之后，形成至少在位置处的给定深度的基板表面处的凹陷（26） 包含对准标记，这些位置被指定为对齐窗口（18），然后在窗口内露出基板的表面，最后进行热氧化步骤以获得场氧化物（19'），在此期间对准 标记（18）同时被氧化物（24）覆盖。

公开(公告)号：US5015598A

公开(公告)日：1991-05-14

申请号：US588116

申请日：1990-09-25

申请人： Robertus D. J. Verhaar

发明人： Robertus D. J. Verhaar

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28247 ,  H01L29/42376 ,  H01L29/7836

摘要： A method is set forth comprising the deposition of a first and a second polycrystalline conducting layer, which are separated by an insulating layer, with the object of creating gate islands which extend in the direction of highly doped parts (22b, 23b) of source and drain zones. According to the invention, the gate islands (15) the first delimited in the first polycrystalline layer (12), after which the edges of these islands are protected with provisional spacers (20a) of an oxidation-preventing material, so that after ion implantation of the weakly doped portions (22, 23) of the source and drain, non-protected parts of the device can be re-oxidized. After this, the provisional spacers (20a) are removed and the second polycrystalline layer (30) is deposited, thus achieving electrical contact with the previously protected edges of the islands (15) of the first polycrystalline layer (12). Widened gate islands are finally formed by the insulating spacer technique (32).

摘要翻译： 提出了一种方法，其包括由绝缘层分离的第一和第二多晶导体层的沉积，其目的是产生沿着源的高度掺杂部分（22b，23b）的方向延伸的栅极岛，以及 排水区。 根据本发明，首先在第一多晶层（12）中限定的栅极岛（15）之后，这些岛的边缘被防氧化材料的临时间隔物（20a）保护，使得在离子注入 的源极和漏极的弱掺杂部分（22,23）可以再次氧化器件的未被保护的部分。 之后，去除临时间隔物（20a）并沉积第二多晶层（30），从而实现与先前保护的第一多晶层（12）的岛状物（15）的边缘的电接触。 最终通过绝缘间隔物技术（32）形成扩大的栅极岛。

公开(公告)号：US5063169A

公开(公告)日：1991-11-05

申请号：US531825

申请日：1990-06-01

申请人： Leendert De Bruin ,  Robertus D. J. Verhaar ,  Josephus M. F. G. Van Laarhoven

发明人： Leendert De Bruin ,  Robertus D. J. Verhaar ,  Josephus M. F. G. Van Laarhoven

IPC分类号： H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L24/11 ,  H01L21/76885 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10S148/026 ,  Y10S438/903

摘要： Electrical connection to a device region (3,4) of a semiconductor device is formed by providing a semiconductor body (1) having adjacent one major surface (12) a device region (3,4) bounded by an insulating region (19a,19b,9), providing an activating layer (11) on the one major surface (12), applying a flowable material as a layer (13) of photosensitive resist, exposing and developing the resist to define an opening (14) over a contact area (12a) of the device region (3,4), and selectively plating electrically conductive material into the opening (14) to form a conductive pillar (15) in electrical contact with the contatct area (12a). The layer (13) of photosensitive resist is removed after formation of the conductive pillar (15) and a layer of insulating material is then provided to cover the conductive pillar (15) and the surface (12). The insulating layer is then etched to expose a top surface (15a) of the conductive pillar (15).

公开(公告)号：US5879990A

公开(公告)日：1999-03-09

申请号：US814868

申请日：1997-03-11

申请人： Guido J. M. Dormans ,  Robertus D. J. Verhaar ,  Roger Cuppens

发明人： Guido J. M. Dormans ,  Robertus D. J. Verhaar ,  Roger Cuppens

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/43 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/42324

摘要： The invention relates in particular, though not exclusively, to an integrated circuit with an embedded non-volatile memory with floating gate (10). According to the invention, at least two poly layers of equal or at least substantially equal thickness are used for this device. The first poly layer, poly A, is for the floating gate (10) and for the gates (22) of NMOS and PMOS in the logic portion of the circuit. The second poly layer, poly B, serves exclusively for the control electrode (21) above the floating gate. If so desired, a third poly layer may be deposited for both the control electrode and the logic gates, so that the thicknesses of these electrodes, and thus their resistances, are given desired values. Problems like overetching and bridging during saliciding are prevented in that the control electrode and the logic gates have the same thickness.

摘要翻译： 本发明特别涉及具有带有浮动栅极（10）的嵌入式非易失性存储器的集成电路（尽管并非排他地）。 根据本发明，对于该装置使用至少两个相等或至少基本相等厚度的多层。 第一多晶硅层poly是用于浮置栅极（10）和电路的逻辑部分中的NMOS和PMOS的栅极（22）。 第二多晶硅层poly B专门用于浮栅之上的控制电极（21）。 如果需要，可以为控制电极和逻辑门两者沉积第三多晶硅层，使得这些电极的厚度以及因此它们的电阻被赋予所需的值。 由于控制电极和逻辑门具有相同的厚度，所以防止了在浇注过程中过蚀刻和桥接的问题。

公开(公告)号：US5015599A

公开(公告)日：1991-05-14

申请号：US588118

申请日：1990-09-25

申请人： Robertus D. J. Verhaar

发明人： Robertus D. J. Verhaar

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/7836

摘要： Method is set forth of manufacturing a device comprising MIS transistors having a projecting gate on the weakly doped parts of source and drain regions.A method comprising the deposition of a first and a second polycrystalline conducting layer, which are separated by an insulating layer.According to the invention, gate islands (20) are formed in the second polycrystalline layer (14) and the ion implantation of the weakly doped portions (21, 22) of the source and drain zones is effected through the assembly of the insulating layer (13) and the first polycrystalline layer (12). A third polycrystalline layer (23) is then deposited, which layer contacts both the island of the second polycrystalline layer (14) and the first polycrystalline layer (12). Widened gate islands (26) are finally marked off by means of the insulating spacer technique (25), in which islands there remain only present the portions (23') of the third polycrystalline layer (23) in the shape of an "L". The highly doped portions (28, 29) of the source and drain zones are then implanted.

摘要翻译： 阐述制造包括在源区和漏区的弱掺杂部分上具有突出栅极的MIS晶体管的器件的方法。 一种包括沉积由绝缘层分离的第一和第二多晶导体层的方法。 根据本发明，在第二多晶层（14）中形成栅极岛（20），并且通过绝缘层的组装来实现源极和漏极区的弱掺杂部分（21,22）的离子注入 13）和第一多晶层（12）。 然后沉积第三多晶层（23），该层与第二多晶层（14）的岛和第一多晶层（12）接触。 扩大的栅极岛（26）最终通过绝缘间隔物技术（25）被标记，其中仅存在第三多晶层（23）的部分（23'）为“L”形的岛， 。 然后植入源区和漏区的高掺杂部分（28,29）。

公开(公告)号：US4489357A

公开(公告)日：1984-12-18

申请号：US371039

申请日：1982-04-23

申请人： Johannes A. C. Van Ooijen ,  Robertus D. J. Verhaar

发明人： Johannes A. C. Van Ooijen ,  Robertus D. J. Verhaar

IPC分类号： G01R33/09 ,  G11B5/39 ,  H01L43/08 ,  G11B5/12 ,  G11B5/25

CPC分类号： G11B5/3925 ,  H01L43/08

摘要： A magnetic sensor (1) includes a magneto-resistive element (3) which magnetically bridges a gap (15) between two magnetic flux conductors (6,7). In order to reduce the noise level and higher harmonic distortion of the sensor, each of the flux conductors (6,7) includes at least two layers (16,18) of magnetically permeable materials having substantially the same composition between which a layer (17) is present which has a different composition.

摘要翻译： 磁传感器（1）包括一磁阻元件（3），该磁阻元件磁耦合两个磁通导体（6,7）之间的间隙（15）。 为了降低传感器的噪声水平和较高的谐波失真，每个磁通导体（6,7）包括至少两层具有基本上相同组成的导磁材料层（16,18），层之间 ），其具有不同的组成。

公开(公告)号：US06326661B1

公开(公告)日：2001-12-04

申请号：US09616630

申请日：2000-07-26

申请人： Guido J. M. Dormans ,  Robertus D. J. Verhaar

发明人： Guido J. M. Dormans ,  Robertus D. J. Verhaar

IPC分类号： H01L29788

CPC分类号： H01L27/115 ,  H01L29/42328

摘要： A semiconductor device comprises a semiconductor body (1) having a region (2) of a first conductivity type adjoining a surface (3) of the semiconductor body (1), which semiconductor body (1) is provided at the surface (3) with a non-volatile memory cell. The memory cell comprises a source (4) and a drain (5) of an opposite, second conductivity type provided in the semiconductor body (1), between which source (4) and drain (5) the surface (3) of the semiconductor body (1) is provided with a floating gate (6) and a select gate (10). The floating gate (6) and the select gate (10) both have a substantially flat surface portion (13) extending substantially parallel to the surface (3) of the semiconductor body (1) and side-wall portions (14) extending substantially transversely to the surface (3) of the semiconductor body (1). A control gate (7) is situated above the floating gate (6), and is capacitively coupled to the substantially flat surface portion (13) of the floating gate (6) and to at least the side-wall portions (14) of the floating gate (6) facing the source (4) and the drain (5). Moreover, the control gate (7) overlaps the select gate (10) and ends above the substantially flat surface portion (13) of the select gate (10).

摘要翻译： 一种半导体器件包括具有邻接半导体本体（1）的表面（3）的第一导电类型的区域（2）的半导体本体（1），该半导体本体（1）设置在表面（3）处， 非易失性存储单元。 存储单元包括设置在半导体本体（1）中的相对的第二导电类型的源极（4）和漏极（5），源极（4）和漏极（5）之间的半导体器件的表面（3） 主体（1）设置有浮动门（6）和选择门（10）。 浮动栅极（6）和选择栅极（10）都具有基本上平行于半导体本体（1）的表面（3）延伸的基本平坦的表面部分（13），并且基本横向延伸的侧壁部分 到半导体本体（1）的表面（3）。 控制栅极（7）位于浮动栅极（6）的上方，并且电容耦合到浮动栅极（6）的基本上平坦的表面部分（13）并且至少连接到浮动栅极（6）的侧壁部分（14） 浮动栅极（6）面向源极（4）和漏极（5）。 此外，控制栅极（7）与选择栅极（10）重叠并且结束在选择栅极（10）的基本上平坦的表面部分（13）之上。

公开(公告)号：US06174759B1

公开(公告)日：2001-01-16

申请号：US09304412

申请日：1999-05-03

申请人： Robertus D. J. Verhaar ,  Joachim C. H. Garbe ,  Guido J. M. Dormans

发明人： Robertus D. J. Verhaar ,  Joachim C. H. Garbe ,  Guido J. M. Dormans

IPC分类号： H01L218234

CPC分类号： H01L27/11526 ,  H01L27/11546

摘要： In the manufacture of integrated circuits with an embedded non-volatile memory, it is known to first provide the greater part of the memory and subsequently provide the CMOS logic in a second series of steps of a standard CMOS process. By virtue of this separation of process steps, it is possible to optimize the non-volatile memory substantially without degrading the logic. According to the invention, this process is further optimized in that, particularly for the periphery of the memory, and simultaneously with the memory transistors (21, 24, 27), transistors are manufactured which can cope with a higher voltage than the transistors of the logic. In the case of an EEPROM, each cell of the memory is provided with such a high-voltage transistor as a selection transistor (22, 24). Apart from the n-well implantation (5), high-voltage transistors of the p-channel are largely manufactured by means of the same process steps as the p-channel transistors in the logic, so that the number of process steps remains limited. By adding a single mask, the circuit may also be provided with a Flash or an OTP (One Time Programmable) memory.

摘要翻译： 在具有嵌入式非易失性存储器的集成电路的制造中，已知首先提供大部分存储器，并随后在标准CMOS工艺的第二系列步骤中提供CMOS逻辑。 由于处理步骤的这种分离，可以基本上不劣化逻辑来优化非易失性存储器。 根据本发明，该方法进一步优化，特别是对于存储器的周边，并且与存储晶体管（21,24,27）同时地，制造了能够处理比该晶体管的晶体管更高的电压的晶体管 逻辑。 在EEPROM的情况下，存储器的每个单元设置有作为选择晶体管（22,24）的这种高压晶体管。 除了n阱注入（5）之外，p沟道的高电压晶体管通过与逻辑中的p沟道晶体管相同的工艺步骤大量制造，使得工艺步骤的数量仍然有限。 通过添加单个掩模，电路还可以设置有闪存或OTP（一次可编程）存储器。

公开(公告)号：US06069033A

公开(公告)日：2000-05-30

申请号：US44544

申请日：1998-03-19

申请人： Robertus D. J. Verhaar ,  Guido J. M. Dormans

发明人： Robertus D. J. Verhaar ,  Guido J. M. Dormans

IPC分类号： H01L21/8238 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11526 ,  H01L21/8238 ,  H01L27/105 ,  H01L27/11546

摘要： The invention provides a method of combining an EPROM (or EEPROM) with a standard CMOS process. After growing the gate oxide 9, a lightly doped polycrystalline or amorphous silicon layer 10, hereinafter referred to as poly I, is deposited. In this layer, the floating gate 13 of the memory cells is defined, while, outside the memory matrix, the surface remains covered with poly I. Subsequently, the source/drain implantation in the memory cells is carried out. The poly layer 10 situated outside the memory matrix is masked against this heavy implantation by the mask 11. Subsequently, a second poly layer can be provided from which the control gates of the memory cells are formed and which forms a coherent layer with the existing poly I layer outside the matrix. In a subsequent series of steps in a standard CMOS process, the n-ch MOSTs and p-ch MOSTs are provided, n-type gates 22 for the n-ch MOSTs and p-type gates 23 for the p-ch MOSTs being formed from the poly I layer.

摘要翻译： 本发明提供了一种将EPROM（或EEPROM）与标准CMOS工艺组合的方法。 在生长栅极氧化物9之后，沉积轻掺杂多晶或非晶硅层10（以下称为聚I）。 在该层中，定义了存储单元的浮置栅极13，而在存储器矩阵之外，表面保持被多晶I覆盖。随后，执行存储单元中的源极/漏极注入。 位于存储器矩阵之外的多晶硅层10被掩模11遮蔽以防止这种重度注入。随后，可以提供第二多晶硅层，存储单元的控制栅极从该第二多晶硅层形成，并且与现有的聚 我层叠在矩阵之外。 在标准CMOS工艺中的随后的一系列步骤中，提供n沟道MOST和p沟道MOST，形成用于n沟道MOST的n型栅极22和用于p沟道MOST的p型栅极23 从多层I层。

公开(公告)号：US5371027A

公开(公告)日：1994-12-06

申请号：US29255

申请日：1993-03-10

申请人： Andrew J. Walker ,  Robertus D. J. Verhaar

发明人： Andrew J. Walker ,  Robertus D. J. Verhaar

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L21/266

CPC分类号： H01L21/28176 ,  H01L21/28273 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/7882

摘要： Very thin tunnel oxides are used in conventional non-volatile memories to obtain a sufficiently strong tunnelling current to or from the floating gate. Usual thicknesses of the tunnel oxide lie in the 8-10 nm range.The invention renders it possible to use tunnel oxides of a much greater thickness, for example of the order of 20 nm, for comparable tunnelling current values. According to the invention, the tunnelling effect is enhanced by implantation of a heavy, high-energy ion, for example As, into a comparatively thin poly layer of the oxide. During this, Si atoms are propelled from the polylayer into the oxide, so that the oxide is enriched with Si, which causes a major change in the tunnelling characteristics. The same oxide which functions as a gate oxide elsewhere may be used for the tunnel oxide. An important advantage of the invention is that direct contact between the tunnel oxide and photoresist layers necessary during the process is avoided, so that the properties of the tunnel oxide are not or at least substantially not impaired by the photoresist.

摘要翻译： 在常规的非易失性存储器中使用非常薄的隧道氧化物以获得足够强的隧道电流到浮栅或从浮栅。 隧道氧化物的通常厚度在8-10nm范围内。 本发明使得可以使用更大厚度的隧道氧化物，例如大约20nm的隧道氧化物，用于可比的隧道电流值。 根据本发明，通过将重的高能离子（例如As）注入到氧化物的相对薄的多层中来增强隧道效应。 在此期间，Si原子从多层推进到氧化物中，使得氧化物富集Si，这导致隧道特性的重大变化。 用作其他地方的栅极氧化物的相同氧化物可用于隧道氧化物。 本发明的一个重要优点是避免了在该过程中所需的隧道氧化物和光致抗蚀剂层之间的直接接触，使得隧道氧化物的性质不被光致抗蚀剂或至少基本上不受光致抗蚀剂的损害。