公开(公告)号：US20130176798A1

公开(公告)日：2013-07-11

申请号：US13769542

申请日：2013-02-18

Applicant: Apple Inc.

Inventor： Edward M. McCombs

IPC: G11C7/22 ,  G11C7/12

CPC classification number: G11C7/22 ,  G11C7/12 ,  G11C8/18

Abstract: A mechanism for managing peak power in a memory storage array that includes sub-array blocks may reduce the peak currents associated with read and write operations by staggering the wordline signal activation to each of the sub-array blocks. In particular, the wordline units within each sub-array block may generate the wordline signals to each sub-array block such that a read wordline signal of one sub-array block does not transition from one logic level to another logic level at the same time as the write wordline of another sub-array block. Further, the wordline units may generate the wordline signals to each sub-array block such that a read wordline of a given sub-array block does not transition from one logic level to another logic level at the same time as a read wordline signal of another sub-array block.

Abstract translation: 用于管理包括子阵列块的存储器阵列中的峰值功率的机制可以通过将字线信号激活交错到每个子阵列块来减少与读取和写入操作相关联的峰值电流。 特别地，每个子阵列块内的字线单元可以向每个子阵列块产生字线信号，使得一个子阵列块的读取字线信号不会同时从一个逻辑电平转换到另一个逻辑电平 作为另一个子阵列块的写字线。 此外，字线单元可以向每个子阵列块产生字线信号，使得给定子阵列块的读取字线不会与另一个逻辑电平的读取字线信号同时从一个逻辑电平转换到另一个逻辑电平 子阵列块。

公开(公告)号：US11803480B2

公开(公告)日：2023-10-31

申请号：US17662500

申请日：2022-05-09

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

CPC classification number: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/144 ,  G11C5/148 ,  G11C7/1006 ,  G11C8/06 ,  G11C11/419

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US10691610B2

公开(公告)日：2020-06-23

申请号：US16124166

申请日：2018-09-06

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US20170256292A1

公开(公告)日：2017-09-07

申请号：US15058631

申请日：2016-03-02

Applicant: Apple Inc.

Inventor： Edward M. McCombs

IPC: G11C5/14 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/417 ,  G11C2207/2227

Abstract: Systems, apparatuses, and methods for implementing a storage array with a voltage regulator circuit. An integrated circuit (IC) may include a storage array, periphery logic, and a voltage regulator circuit coupled to an array power supply and a periphery power supply; the latter may operate at any of several periphery operating voltages according to respective power modes of operation. One or more of the periphery operating voltages may be less than a threshold array operating voltage that is required by the storage array for read or write access during an active mode of storage array operation. The voltage regulator circuit may generate, dependent on a selected power mode, a regulated array power supply that operates at a voltage that satisfies the threshold array operating voltage and is less than an operating voltage of the array power supply. The regulated power supply may reduce overall power consumption of the storage array.

公开(公告)号：US20140198594A1

公开(公告)日：2014-07-17

申请号：US13739546

申请日：2013-01-11

Applicant: APPLE INC.

Inventor： Edward M. McCombs

IPC: G11C7/12

CPC classification number: G11C7/12

Abstract: Embodiments of a memory device are disclosed that may allow for multiple pre-charge voltages. The memory device may include a plurality of data lines, and a plurality of pre-charge circuits. Each of the plurality of data lines may be coupled to a plurality of data storage cells. Each of the plurality of pre-charge circuits may be coupled to a respective data line, and be configured to charge the data line to a first voltage level responsive to a first control signal. Each of the plurality of pre-charge circuits may also be configured to charge the respective data line to a second voltage responsive to a second control signal.

Abstract translation: 公开了可以允许多个预充电电压的存储器件的实施例。 存储器件可以包括多条数据线，以及多个预充电电路。 多个数据线中的每一个可以耦合到多个数据存储单元。 多个预充电电路中的每一个可以耦合到相应的数据线，并且被配置为响应于第一控制信号将数据线充电到第一电压电平。 多个预充电电路中的每一个还可以被配置为响应于第二控制信号将相应的数据线充电到第二电压。

公开(公告)号：US20220269617A1

公开(公告)日：2022-08-25

申请号：US17662500

申请日：2022-05-09

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US20180082735A1

公开(公告)日：2018-03-22

申请号：US15271516

申请日：2016-09-21

Applicant: Apple Inc.

Inventor： Edward M. McCombs

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  G06F12/0875

CPC classification number: G11C11/4096 ,  G06F12/0875 ,  G06F19/00 ,  G06F2212/1028 ,  G06F2212/452 ,  G11C5/145 ,  G11C7/1096 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/419

Abstract: Techniques for implementing a storage array write driver with a reduced-power boost circuit. An apparatus may include a bit cell configured to store data, a bit line circuit coupled to convey data to the bit cell, a write driver circuit configured to transmit write data to the bit cell via the bit line circuit, and a boost circuit that is distinct from the write driver circuit. The boost circuit may be selectively coupled to drive the bit line circuit below a ground voltage dependent on activation of a boost signal and the write data being in a logic low state. The boost circuit may also be coupled to the bit line circuit at a location that is closer to the bit cell than to the write driver circuit, and may be sized to discharge the bit line circuit without being sized to discharge internal capacitance of the write driver.

公开(公告)号：US08649240B2

公开(公告)日：2014-02-11

申请号：US13769542

申请日：2013-02-18

Applicant: Apple Inc.

Inventor： Edward M. McCombs

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C7/12 ,  G11C8/18

Abstract: A mechanism for managing peak power in a memory storage array that includes sub-array blocks may reduce the peak currents associated with read and write operations by staggering the wordline signal activation to each of the sub-array blocks. In particular, the wordline units within each sub-array block may generate the wordline signals to each sub-array block such that a read wordline signal of one sub-array block does not transition from one logic level to another logic level at the same time as the write wordline of another sub-array block. Further, the wordline units may generate the wordline signals to each sub-array block such that a read wordline of a given sub-array block does not transition from one logic level to another logic level at the same time as a read wordline signal of another sub-array block.

Abstract translation: 用于管理包括子阵列块的存储器阵列中的峰值功率的机制可以通过将字线信号激活交错到每个子阵列块来减少与读取和写入操作相关联的峰值电流。 特别地，每个子阵列块内的字线单元可以向每个子阵列块产生字线信号，使得一个子阵列块的读取字线信号不会同时从一个逻辑电平转换到另一个逻辑电平 作为另一个子阵列块的写字线。 此外，字线单元可以向每个子阵列块产生字线信号，使得给定子阵列块的读取字线不会与另一个逻辑电平的读取字线信号同时从一个逻辑电平转换到另一个逻辑电平 子阵列块。

公开(公告)号：US20140016392A1

公开(公告)日：2014-01-16

申请号：US14029989

申请日：2013-09-18

Applicant: Apple Inc.

Inventor： Edward M. McCombs ,  Daniel C. Chow ,  Kenneth W. Jones ,  Alexander E. Runas

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C7/06 ,  G11C11/4091 ,  G11C2207/002

Abstract: A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

Abstract translation: 存储器包括在多个存储阵列之间共享的I / O单元。 共享I / O单元提供阵列的输出数据。 存储器包括连接在每个存储阵列和共享I / O单元之间的隔离单元。 此外，每个存储阵列和共享I / O单元可以通过例如电源门控电路连接到单独的开关电压域。 如果一个或多个存储阵列被置于保持或低电压模式，则耦合到受影响的存储阵列的隔离单元可以被配置为将这些存储阵列的位线与共享的I / O数据路径隔离开来。

公开(公告)号：US20130106464A1

公开(公告)日：2013-05-02

申请号：US13717396

申请日：2012-12-17

Applicant: Apple Inc.

Inventor： Edward M. McCombs

IPC: H03K19/096

CPC classification number: H03K19/096 ,  G06F12/1027 ,  G11C7/062 ,  Y02D10/13

Abstract: An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.

Abstract translation: 具有共享门控控制的具有脉冲时钟单元的集成电路包括一个或多个逻辑块，每个逻辑块包括配置成分配时钟信号的时钟分配网络。 该集成电路还包括一个时钟单元，该时钟单元耦合到该一个或多个逻辑块并被配置为产生使用反相逻辑门链形成的脉冲时钟信号。 时钟单元还可以被配置为向时钟分配网络提供脉冲时钟信号。 时钟单元还可以包括耦合到反相逻辑门之一的一个输入的使能输入。 此外，时钟单元可以被配置为响应于使能输入上的使能信号选择性地启用和禁用脉冲时钟信号。