公开(公告)号：US11487667B1

公开(公告)日：2022-11-01

申请号：US17397429

申请日：2021-08-09

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US20230084736A1

公开(公告)日：2023-03-16

申请号：US17933603

申请日：2022-09-20

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US10678542B2

公开(公告)日：2020-06-09

申请号：US14808811

申请日：2015-07-24

Applicant: Apple Inc.

Inventor： Ian D. Kountanis ,  Mahesh K. Reddy

IPC: G06F9/30

Abstract: Systems, apparatuses, and methods for implementing a non-shifting reservation station. A dispatch unit may write an operation into any entry of a reservation station. The reservation station may include an age matrix for determining the relative ages of the operations stored in the entries of the reservation station. The reservation station may include selection logic which is configured to pick the oldest ready operation from the reservation station based on the values stored in the age matrix. The selection logic may utilize control logic to mask off columns of an age matrix corresponding to non-ready operation so as to determine which operation is the oldest ready operation in the reservation station. Also, the reservation station may be configured to dequeue operations early when these operations do not have load dependency.

公开(公告)号：US20170024205A1

公开(公告)日：2017-01-26

申请号：US14808811

申请日：2015-07-24

Applicant: Apple Inc.

Inventor： Ian D. Kountanis ,  Mahesh K. Reddy

IPC: G06F9/30

Abstract: Systems, apparatuses, and methods for implementing a non-shifting reservation station. A dispatch unit may write an operation into any entry of a reservation station. The reservation station may include an age matrix for determining the relative ages of the operations stored in the entries of the reservation station. The reservation station may include selection logic which is configured to pick the oldest ready operation from the reservation station based on the values stored in the age matrix. The selection logic may utilize control logic to mask off columns of an age matrix corresponding to non-ready operation so as to determine which operation is the oldest ready operation in the reservation station. Also, the reservation station may be configured to dequeue operations early when these operations do not have load dependency.

Abstract translation: 用于实施非移动保留站的系统，装置和方法。 调度单元可以将操作写入保留站的任何条目。 保留站可以包括用于确定存储在保留站的条目中的操作的相对年龄的年龄矩阵。 保留站可以包括选择逻辑，其被配置为基于存储在年龄矩阵中的值从保留站中选择最早的就绪操作。 选择逻辑可以利用控制逻辑来屏蔽对应于未就绪操作的年龄矩阵的列，以便确定哪个操作是保留站中的最早的就绪操作。 此外，保留站可以被配置为当这些操作没有负载依赖性时提前出队。

公开(公告)号：US10747535B1

公开(公告)日：2020-08-18

申请号：US15207115

申请日：2016-07-11

Applicant: Apple Inc.

Inventor： Mahesh K. Reddy ,  Matthew C. Stone

IPC: G06F9/30 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/084 ,  G06F12/0875

Abstract: Systems, apparatuses, and methods for processing load instructions are disclosed. A processor includes at least a data cache and a load queue for storing load instructions. The load queue includes poison indicators for load instructions waiting to reach non-speculative status. When a non-cacheable load instruction is speculatively executed, then the poison bit is automatically set for the load instruction. If a cacheable load instruction is speculatively executed, then the processor waits until detecting a first condition before setting the poison bit for the load instruction. The first condition may be detecting a cache line with data for the load instruction being evicted from the cache. If an ordering event occurs for a load instruction with a set poison bit, then the load instruction may be flushed and replayed. An ordering event may be a data barrier or a hazard on an older load targeting the same address as the load.

公开(公告)号：US10402326B1

公开(公告)日：2019-09-03

申请号：US15138666

申请日：2016-04-26

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mahesh K. Reddy ,  David J. Williamson

IPC: G06F12/0815

Abstract: A system that includes circuitry to access memories in both coherent and non-coherent domains is disclosed. The circuitry may receive a command to access a memory included in the coherent domain and generate one or more commands to access a memory in the non-coherent domain dependent upon the received command. The circuitry may send the generated one or more commands to the memory in the non-coherent domain via communication bus.

公开(公告)号：US20240176744A1

公开(公告)日：2024-05-30

申请号：US18438111

申请日：2024-02-09

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6032

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US11880308B2

公开(公告)日：2024-01-23

申请号：US17933603

申请日：2022-09-20

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6032

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US20230017473A1

公开(公告)日：2023-01-19

申请号：US17373814

申请日：2021-07-13

Applicant: APPLE INC.

Inventor： John D. Pape ,  Mahesh K. Reddy ,  Prasanna Utchani Varadharajan ,  Pruthivi Vuyyuru

IPC: G06F12/0802

Abstract: An apparatus includes multiple processors including respective cache memories, the cache memories configured to cache cache-entries for use by the processors. At least a processor among the processors includes cache management logic that is configured to (i) receive, from one or more of the other processors, cache-invalidation commands that request invalidation of specified cache-entries in the cache memory of the processor (ii) mark the specified cache-entries as intended for invalidation but defer actual invalidation of the specified cache-entries, and (iii) upon detecting a synchronization event associated with the cache-invalidation commands, invalidate the cache-entries that were marked as intended for invalidation.

公开(公告)号：US11422821B1

公开(公告)日：2022-08-23

申请号：US16120675

申请日：2018-09-04

Applicant: Apple Inc.

Inventor： James N. Hardage, Jr. ,  Christopher M. Tsay ,  Mahesh K. Reddy

IPC: G06F9/38 ,  G06F9/30

Abstract: A system and method for efficiently handling instruction execution ordering. In various embodiments, a processor includes multiple execution lanes, each executing instructions of a particular type, which are not executed by one or more of the other execution lanes. The instruction queue includes one queue for each particular execution lane. Control logic identifies a current youngest age used in allocated entries of the multiple queues, and determines a starting age based on the identified current youngest age and the number of instructions to be issued. Beginning with the determined starting age, ages (in program order) are assigned to a group of instructions being allocated in the multiple queues. Ages of entries in the multiple queues are updated for instructions not being issued based on the number of instructions being issued. Instructions being issued have age differences between them below a threshold.