公开(公告)号：US20160085900A1

公开(公告)日：2016-03-24

申请号：US14492923

申请日：2014-09-22

Applicant: Apple Inc.

Inventor： Amit Chandra ,  Karthik Rajagopal ,  Muthukumaravelu Velayoudame ,  Praveen Bhutani ,  Sunil Mehta

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5036 ,  G06F17/5081 ,  G06F2217/78

Abstract: In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.

Abstract translation: 在一个实施例中，提供了一种用于设计试图提高功率效率的集成电路的方法。 该方法包括模拟在一个或多个功率刺激下的设计，其中功率刺激已知导致高功率消耗（例如在集成电路的先前设计中，功率刺激可能已经引起功率消耗）。 在集成电路中可以识别出在仿真中具有最高活动性（例如最高切换量）的网络集合。 该方法可以包括向布线工具提供数据以将集线器中的网络路由。 数据可能表示网络集合的约束，以帮助减少这些网络的动态功率。 如果路由工具能够遵守约束，则可以提高集成电路的功率效率。

公开(公告)号：US09824171B2

公开(公告)日：2017-11-21

申请号：US14820223

申请日：2015-08-06

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Mridul Agarwal ,  Shyam Sundar Balasubramanian ,  Christopher S. Thomas ,  Rajat Goel ,  Rohit Kumar ,  Muthukumaravelu Velayoudame

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5068

Abstract: In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.

公开(公告)号：US20170039299A1

公开(公告)日：2017-02-09

申请号：US14820223

申请日：2015-08-06

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Mridul Agarwal ,  Shyam Sundar Balasubramanian ,  Christopher S. Thomas ,  Rajat Goel ,  Rohit Kumar ,  Muthukumaravelu Velayoudame

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5068

Abstract: In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.

Abstract translation: 在一些实施例中，寄存器文件电路设计过程包括指示自动集成电路设计程序产生寄存器文件电路设计，包括提供单元电路设计并指示自动化集成电路设计程序产生选择设计，预解码 设计和数据门控设计。 单元电路设计描述了具有特定布置的多个选择电路。 选择设计描述了包括具有特定布置的相应多个选择电路的多个复制电路。 预解码设计描述了预解码电路，其被配置为识别由写指令的一部分识别的多个条目。 数据门控设计描述了数据选通电路，其响应于未识别相应条目的预解码电路而配置，以禁止连接到各个条目的相应写入选择电路的数据输入。

公开(公告)号：US09292648B1

公开(公告)日：2016-03-22

申请号：US14492923

申请日：2014-09-22

Applicant: Apple Inc.

Inventor： Amit Chandra ,  Karthik Rajagopal ,  Muthukumaravelu Velayoudame ,  Praveen Bhutani ,  Sunil Mehta

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5036 ,  G06F17/5081 ,  G06F2217/78

Abstract: In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.

Abstract translation: 在一个实施例中，提供了一种用于设计试图提高功率效率的集成电路的方法。 该方法包括模拟在一个或多个功率刺激下的设计，其中功率刺激已知导致高功率消耗（例如在集成电路的先前设计中，功率刺激可能已经引起功率消耗）。 在集成电路中可以识别出在仿真中具有最高活动性（例如最高切换量）的网络集合。 该方法可以包括向布线工具提供数据以将集线器中的网络路由。 数据可能表示网络集合的约束，以帮助减少这些网络的动态功率。 如果路由工具能够遵守约束，则可以提高集成电路的功率效率。

公开(公告)号：US09513658B2

公开(公告)日：2016-12-06

申请号：US14641619

申请日：2015-03-09

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Muthukumaravelu Velayoudame

IPC: G06F1/10 ,  G06F1/14 ,  G06F17/50 ,  H03K19/00

CPC classification number: G06F1/10 ,  G06F1/14 ,  G06F17/5022 ,  G06F17/5031 ,  H03K19/0016

Abstract: A process utilized in an integrated circuit design methodology may be used to assess and organize individual bits (e.g., flip-flops) within multi-bit clocked storage devices (e.g., multi-bit flip-flops) for use in the integrated circuit design. The process may include assessing timing slacks of the bits, sorting and/or assigning the bits based on the assessed timing slacks, and remapping the multi-bit clocked storage devices using the sorted and/or assigned bits. One or more timing corrections may be applied to the remapped multi-bit clocked storage devices. The timing corrections may include useful clock skewing or resizing (e.g., upsizing or downsizing) of the remapped multi-bit clocked storage devices.

Abstract translation: 在集成电路设计方法中使用的过程可以用于评估和组织用于集成电路设计的多位定时存储设备（例如，多位触发器）内的各个位（例如，触发器）。 该过程可以包括基于所评估的定时松弛来评估比特的定时松弛，排序和/或分配比特，以及使用排序和/或分配的比特重新映射多比特定时存储的设备。 重新映射的多位定时存储设备可以应用一个或多个定时校正。 定时校正可以包括有用的时钟偏移或调整重映射的多位定时存储设备的大小（例如，增大或缩小尺寸）。

公开(公告)号：US20160266604A1

公开(公告)日：2016-09-15

申请号：US14641619

申请日：2015-03-09

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Muthukumaravelu Velayoudame

IPC: G06F1/10 ,  G06F1/14

CPC classification number: G06F1/10 ,  G06F1/14 ,  G06F17/5022 ,  G06F17/5031 ,  H03K19/0016

Abstract: A process utilized in an integrated circuit design methodology may be used to assess and organize individual bits (e.g., flip-flops) within multi-bit clocked storage devices (e.g., multi-bit flip-flops) for use in the integrated circuit design. The process may include assessing timing slacks of the bits, sorting and/or assigning the bits based on the assessed timing slacks, and remapping the multi-bit clocked storage devices using the sorted and/or assigned bits. One or more timing corrections may be applied to the remapped multi-bit clocked storage devices. The timing corrections may include useful clock skewing or resizing (e.g., upsizing or downsizing) of the remapped multi-bit clocked storage devices.

Abstract translation: 在集成电路设计方法中使用的过程可以用于评估和组织用于集成电路设计的多位定时存储设备（例如，多位触发器）内的各个位（例如，触发器）。 该过程可以包括基于所评估的定时松弛来评估比特的定时松弛，排序和/或分配比特，以及使用排序和/或分配的比特重新映射多比特定时存储的设备。 重新映射的多位定时存储设备可以应用一个或多个定时校正。 定时校正可以包括有用的时钟偏移或调整重映射的多位定时存储设备的大小（例如，增大或缩小尺寸）。