公开(公告)号：US20180181491A1

公开(公告)日：2018-06-28

申请号：US15389153

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Luc R. Semeria ,  Gokhan Avkarogullari ,  David A. Gotwalt ,  Robert S. Hartog ,  Michael J. Swift

IPC: G06F12/0891 ,  G06F12/0895

CPC classification number: G06F12/0891 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/1063 ,  G06F12/109 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/60 ,  G06F2212/657

Abstract: Techniques are disclosed relating to flushing cache lines. In some embodiments, a graphics processing unit includes a cache and one or more storage elements configured to store a plurality of command buffers that include instructions executable to manipulate data stored in the cache. In some embodiments, ones of the cache lines in the cache are configured to store data to be operated on by instructions in the command buffers and a first tag portion that identifies a command buffer that has stored data in the cache line. In some embodiments, the graphics processing unit is configured to receive a request to flush cache lines that store data of a particular command buffer, and to flush ones of the cache lines having first tag portions indicating the particular command buffer as having data stored in the cache lines while maintaining data stored in other ones of the cache lines as valid.

公开(公告)号：US20210074053A1

公开(公告)日：2021-03-11

申请号：US16953021

申请日：2020-11-19

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Michael J. Swift ,  Michal Valient ,  Robert S. Hartog ,  Tyson J. Bergland ,  Gokhan Avkarogullari

IPC: G06T15/04 ,  G06T1/60 ,  G06F9/38 ,  G06T11/00 ,  G06F12/1009 ,  G06F9/50 ,  G06T15/00 ,  G06F12/0811

Abstract: Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.

公开(公告)号：US11257278B2

公开(公告)日：2022-02-22

申请号：US16953021

申请日：2020-11-19

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Michael J. Swift ,  Michal Valient ,  Robert S. Hartog ,  Tyson J. Bergland ,  Gokhan Avkarogullari

IPC: G06F12/1009 ,  G06T1/60 ,  G06T15/04 ,  G06F9/38 ,  G06T15/00 ,  G06F12/0811 ,  G06F9/50 ,  G06T11/00

Abstract: Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.

公开(公告)号：US20190244323A1

公开(公告)日：2019-08-08

申请号：US15887547

申请日：2018-02-02

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Christopher L. Spencer ,  Mark D. Earl ,  Robert S. Hartog ,  Timothy M. Kelley

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06T1/20 ,  G06F9/30101 ,  G06F9/3867

Abstract: Techniques are disclosed relating to processing groups of graphics work (which may be referred to as “kicks”) using a graphics processing pipeline. In some embodiments, a graphics processor includes multiple sets of configuration registers such that multiple kicks can be processed in the pipeline at the same time. In some embodiments, kicks are pipelined such that a subsequent kick ramps up use of hardware resources as a previous kick winds down. In some embodiments, the graphics processing may execute kicks concurrently and/or preemptively, e.g., based on a priority scheme. In some embodiments, the disclosed techniques may be used with pipelines that include front and back-end fixed function circuitry as well as shared programmable resources such as shader cores. In various embodiments, the disclosed techniques may improve overall performance and/or reduce latency for high-priority graphics tasks.