Unified address translation
    1.
    发明授权

    公开(公告)号:US11221962B2

    公开(公告)日:2022-01-11

    申请号:US16874997

    申请日:2020-05-15

    Applicant: Apple Inc.

    Abstract: A system and method for efficiently transferring address mappings and data access permissions corresponding to the address mappings. A computing system includes at least one processor and memory for storing a page table. In response to receiving a memory access operation comprising a first address, the address translation unit is configured to identify a data access permission based on a permission index corresponding to the first address, and access data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission. The address translation unit is configured to access a table to identify the data access permission, and is configured to determine the permission index and the second address based on the first address. A single permission index may correspond to different permissions for different entities within the system.

    Graphics Driver Virtual Channels for Out-of-Order Command Scheduling for a Graphics Processor

    公开(公告)号:US20200104968A1

    公开(公告)日:2020-04-02

    申请号:US16202689

    申请日:2018-11-28

    Applicant: Apple Inc.

    Abstract: Systems, methods, and computer readable media to perform out-of-order command scheduling for a graphics processor are described. A graphics driver receives commands committed to a graphics processor for execution. The graphics driver queues a first command to a first graphics driver virtual channel that submits commands to the graphics processor for execution. The first command is associated with a first set of resources. The graphics driver determines whether a second set of resources associated with the second command depends on the first set of resources. The graphics driver queues the second command to the first graphics driver virtual channel based on a determination that the second set of resources depends on the first set of resources. The graphics driver queues the second command to a second virtual channel based on a determination that the second set of resources does not depend on the first set of resources.

    Memory consistency in graphics memory hierarchy with relaxed ordering

    公开(公告)号:US10324844B2

    公开(公告)日:2019-06-18

    申请号:US15389047

    申请日:2016-12-22

    Applicant: Apple Inc.

    Abstract: Techniques are disclosed relating to memory consistency in a memory hierarchy with relaxed ordering. In some embodiments, an apparatus includes a first level cache that is shared by a plurality of shader processing elements and a second level cache that is shared by the shader processing elements and at least a texture processing unit. In some embodiments, the apparatus is configured to execute operations specified by graphics instructions that include (1) an attribute of the operation that specifies a type of memory consistency to be imposed for the operation and (2) scope information for the attribute that specifies whether the memory consistency specified by the attribute should be enforced at the first level cache or the second level cache. In some embodiments, the apparatus is configured to determine whether to sequence memory accesses at the first level cache and the second level cache based on the attribute and the scope.

    TEXTURE NOT BACKED BY REAL MAPPING
    6.
    发明申请

    公开(公告)号:US20170358055A1

    公开(公告)日:2017-12-14

    申请号:US15587063

    申请日:2017-05-04

    Applicant: Apple Inc.

    CPC classification number: G06T1/60 G06T1/20 G06T15/005

    Abstract: One disclosed embodiment includes memory allocation methods for use by a graphics processing unit in rendering graphics data for display. The method includes receiving a buffer attachment associated with a first rendering pass. The hardware prerequisites for operation of the first rendering pass is determined. The method also includes receiving an indication to not allocate system memory for the received buffer attachment. Thereafter, it may be determined whether the received buffer attachment will be loaded from or stored to by the subsequent rendering passes. If it is determined that the buffer attachment will be accessed by the subsequent rendering passes, an error message may be generated indicating that system memory must be allocated. If it is determined that the buffer attachment will not be accessed by the subsequent rendering passes, the buffer attachment is rendered without allocating system memory.

    Graphics Surface Addressing
    7.
    发明申请

    公开(公告)号:US20210074053A1

    公开(公告)日:2021-03-11

    申请号:US16953021

    申请日:2020-11-19

    Applicant: Apple Inc.

    Abstract: Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.

    UNIFIED ADDRESS TRANSLATION
    8.
    发明申请

    公开(公告)号:US20210064539A1

    公开(公告)日:2021-03-04

    申请号:US16874997

    申请日:2020-05-15

    Applicant: Apple Inc.

    Abstract: A system and method for efficiently transferring address mappings and data access permissions corresponding to the address mappings. A computing system includes at least one processor and memory for storing a page table. In response to receiving a memory access operation comprising a first address, the address translation unit is configured to identify a data access permission based on a permission index corresponding to the first address, and access data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission. The address translation unit is configured to access a table to identify the data access permission, and is configured to determine the permission index and the second address based on the first address. A single permission index may correspond to different permissions for different entities within the system.

    Graphics driver virtual channels for out-of-order command scheduling for a graphics processor

    公开(公告)号:US10692169B2

    公开(公告)日:2020-06-23

    申请号:US16202689

    申请日:2018-11-28

    Applicant: Apple Inc.

    Abstract: Systems, methods, and computer readable media to perform out-of-order command scheduling for a graphics processor are described. A graphics driver receives commands committed to a graphics processor for execution. The graphics driver queues a first command to a first graphics driver virtual channel that submits commands to the graphics processor for execution. The first command is associated with a first set of resources. The graphics driver determines whether a second set of resources associated with the second command depends on the first set of resources. The graphics driver queues the second command to the first graphics driver virtual channel based on a determination that the second set of resources depends on the first set of resources. The graphics driver queues the second command to a second virtual channel based on a determination that the second set of resources does not depend on the first set of resources.

    Graphics surface addressing
    10.
    发明授权

    公开(公告)号:US11257278B2

    公开(公告)日:2022-02-22

    申请号:US16953021

    申请日:2020-11-19

    Applicant: Apple Inc.

    Abstract: Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.

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