公开(公告)号：US20230025207A1

公开(公告)日：2023-01-26

申请号：US17880507

申请日：2022-08-03

Applicant: Apple Inc.

Inventor： Charles J. Fleckenstein ,  Tal Lazmi ,  Ori Isachar

IPC: G01R31/317 ,  G01R31/3183 ,  G01R31/319

Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

公开(公告)号：US12093161B2

公开(公告)日：2024-09-17

申请号：US17326114

申请日：2021-05-20

Applicant: Apple Inc.

Inventor： Charles J. Fleckenstein ,  Ori Isachar ,  Tal Lazmi

IPC: G06F11/30 ,  G01R31/317 ,  G06F11/34 ,  G06F13/40

CPC classification number: G06F11/348 ,  G01R31/31705 ,  G06F11/3003 ,  G06F11/3065 ,  G06F11/3485 ,  G06F11/349 ,  G06F11/3495 ,  G06F13/4022 ,  G06F13/4027

Abstract: A trace network for debugging integrated circuits is disclosed. At least one functional network includes a plurality of components interconnected by a number of network switches, implemented on at least one integrated circuit. A trace network is also implemented on the at least one integrated circuit, and includes a plurality of trace circuits configured to generate trace data based on transactions between ones of the plurality of components. The plurality of trace circuits are coupled to one another by a plurality of trace network switches. The trace circuits are configured to convey the generated trace data to an interface, via the trace network, without using the at least one functional network.

公开(公告)号：US11422184B1

公开(公告)日：2022-08-23

申请号：US17230443

申请日：2021-04-14

Applicant: Apple Inc.

Inventor： Charles J. Fleckenstein ,  Tal Lazmi ,  Ori Isachar

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/319

Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

公开(公告)号：US20160371211A1

公开(公告)日：2016-12-22

申请号：US14806795

申请日：2015-07-23

Applicant: APPLE INC.

Inventor： Ori Isachar ,  Gil Semo ,  Guy Kushtai ,  Tal Lazmi

IPC: G06F13/40 ,  G06F13/28

CPC classification number: G06F13/4013 ,  G06F13/16 ,  G06F13/287 ,  G06F13/4022

Abstract: An apparatus for use with a memory device that has a plurality of memory-device terminals having respective unique bit significances is described. The apparatus includes a memory controller, which includes (i) a plurality of external terminals, each one of the external terminals configured to be in communication with a respective one of the memory-device terminals, (ii) a plurality of internal terminals having respective unique bit significances, (iii) a switching unit, and (iv) a processor. The processor is configured to drive the memory device to communicate a predetermined sequence of bit patterns to the controller, and, in response to the sequence of bit patterns, drive the switching unit to connect each one of the external terminals to a respective one of the internal terminals having the bit significance of the memory-device terminal with which the external terminal is in communication. Other embodiments are also described.

Abstract translation: 描述了一种与存储器件一起使用的装置，该装置具有多个具有各自独特的比特重要性的存储器件终端。 该装置包括存储器控制器，其包括（i）多个外部端子，每个外部端子被配置为与相应的一个存储器件端子通信，（ii）多个内部端子具有相应的 独特的比特意义，（iii）切换单元，和（iv）处理器。 处理器被配置为驱动存储器设备以将预定的位模式序列传送到控制器，并且响应于位模式的顺序驱动切换单元将每个外部终端连接到相应的一个 内部终端具有与外部终端进行通信的存储器件终端的位有意义。 还描述了其它实施例。

公开(公告)号：US20250077384A1

公开(公告)日：2025-03-06

申请号：US18886122

申请日：2024-09-16

Applicant: Apple Inc.

Inventor： Charles J. Fleckenstein ,  Ori Isachar ,  Tal Lazmi

IPC: G06F11/34 ,  G01R31/317 ,  G06F11/30 ,  G06F13/40

Abstract: A trace network for debugging integrated circuits is disclosed. At least one functional network includes a plurality of components interconnected by a number of network switches, implemented on at least one integrated circuit. A trace network is also implemented on the at least one integrated circuit, and includes a plurality of trace circuits configured to generate trace data based on transactions between ones of the plurality of components. The plurality of trace circuits are coupled to one another by a plurality of trace network switches. The trace circuits are configured to convey the generated trace data to an interface, via the trace network, without using the at least one functional network.

公开(公告)号：US11946969B2

公开(公告)日：2024-04-02

申请号：US17880507

申请日：2022-08-03

Applicant: Apple Inc.

Inventor： Charles J. Fleckenstein ,  Tal Lazmi ,  Ori Isachar

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/319

CPC classification number: G01R31/31705 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/318314 ,  G01R31/31924

Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

公开(公告)号：US20220374326A1

公开(公告)日：2022-11-24

申请号：US17326114

申请日：2021-05-20

Applicant: Apple Inc.

Inventor： Charles J. Fleckenstein ,  Ori Isachar ,  Tal Lazmi

IPC: G06F11/34 ,  G06F11/30 ,  G06F13/40 ,  G01R31/317

Abstract: A trace network for debugging integrated circuits is disclosed. At least one functional network includes a plurality of components interconnected by a number of network switches, implemented on at least one integrated circuit. A trace network is also implemented on the at least one integrated circuit, and includes a plurality of trace circuits configured to generate trace data based on transactions between ones of the plurality of components. The plurality of trace circuits are coupled to one another by a plurality of trace network switches. The trace circuits are configured to convey the generated trace data to an interface, via the trace network, without using the at least one functional network.