公开(公告)号：US11669480B2

公开(公告)日：2023-06-06

申请号：US17320169

申请日：2021-05-13

Applicant: Apple Inc.

Inventor： Igor Tolchinsky ,  Charles J. Fleckenstein ,  Sagi Lahav ,  Lital Levy-Rubin

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4027 ,  G06F13/4282 ,  G06F2213/0038 ,  G06F2213/0042

Abstract: In an embodiment, an SOC includes a global communication fabric that includes multiple independent networks having different communication and coherency protocols, and a plurality of input-output (I/O) clusters that includes different sets of local functional circuits. A given I/O cluster may be coupled to one or more of the independent networks and may include a particular set of local functional circuits, a local fabric coupled to the particular set of local functional circuits, and an interface circuit coupled to the local fabric and configured to bridge transactions between the particular set of local functional circuits and the global communication fabric. The interface circuit may include a programmable hardware transaction generator circuit configured to generate a set of test transactions that simulate interactions between the particular set of local functional circuits and a particular one of the one or more independent networks.

公开(公告)号：US12189565B2

公开(公告)日：2025-01-07

申请号：US18306087

申请日：2023-04-24

Applicant: Apple Inc.

Inventor： Igor Tolchinsky ,  Charles J. Fleckenstein ,  Sagi Lahav ,  Lital Levy-Rubin

IPC: G06F13/40 ,  G06F13/42

Abstract: In an embodiment, an SOC includes a global communication fabric that includes multiple independent networks having different communication and coherency protocols, and a plurality of input-output (I/O) clusters that includes different sets of local functional circuits. A given I/O cluster may be coupled to one or more of the independent networks and may include a particular set of local functional circuits, a local fabric coupled to the particular set of local functional circuits, and an interface circuit coupled to the local fabric and configured to bridge transactions between the particular set of local functional circuits and the global communication fabric. The interface circuit may include a programmable hardware transaction generator circuit configured to generate a set of test transactions that simulate interactions between the particular set of local functional circuits and a particular one of the one or more independent networks.

公开(公告)号：US20230025207A1

公开(公告)日：2023-01-26

申请号：US17880507

申请日：2022-08-03

Applicant: Apple Inc.

Inventor： Charles J. Fleckenstein ,  Tal Lazmi ,  Ori Isachar

IPC: G01R31/317 ,  G01R31/3183 ,  G01R31/319

Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

公开(公告)号：US11853148B2

公开(公告)日：2023-12-26

申请号：US17656153

申请日：2022-03-23

Applicant: Apple Inc.

Inventor： John H. Kelm ,  Richard H. Larson ,  Charles J. Fleckenstein

IPC: G06F11/07

CPC classification number: G06F11/0757

Abstract: An apparatus includes a memory circuit, and an integrated circuit formed on a single semiconductor substrate and coupled to the memory circuit. The integrated circuit includes a watchdog timer, a plurality of functional circuits coupled together via a communication fabric, and a system management circuit coupled to the watchdog timer and to a subset of the functional circuits via respective dedicated point-to-point interfaces. A given functional circuit may be configured to repeatedly reset the watchdog timer before the watchdog timer expires. The system management circuit may be configured, in response to an expiration of the watchdog timer, to access information in the subset of the functional circuits via the respective point-to-point interfaces. The system management circuit may be further configured to store the accessed information in the memory circuit.

公开(公告)号：US20230089576A1

公开(公告)日：2023-03-23

申请号：US17656153

申请日：2022-03-23

Applicant: Apple Inc.

Inventor： John H. Kelm ,  Richard H. Larson ,  Charles J. Fleckenstein

IPC: G06F11/07

Abstract: An apparatus includes a memory circuit, and an integrated circuit formed on a single semiconductor substrate and coupled to the memory circuit. The integrated circuit includes a watchdog timer, a plurality of functional circuits coupled together via a communication fabric, and a system management circuit coupled to the watchdog timer and to a subset of the functional circuits via respective dedicated point-to-point interfaces. A given functional circuit may be configured to repeatedly reset the watchdog timer before the watchdog timer expires. The system management circuit may be configured, in response to an expiration of the watchdog timer, to access information in the subset of the functional circuits via the respective point-to-point interfaces. The system management circuit may be further configured to store the accessed information in the memory circuit.

公开(公告)号：US12093161B2

公开(公告)日：2024-09-17

申请号：US17326114

申请日：2021-05-20

Applicant: Apple Inc.

Inventor： Charles J. Fleckenstein ,  Ori Isachar ,  Tal Lazmi

IPC: G06F11/30 ,  G01R31/317 ,  G06F11/34 ,  G06F13/40

CPC classification number: G06F11/348 ,  G01R31/31705 ,  G06F11/3003 ,  G06F11/3065 ,  G06F11/3485 ,  G06F11/349 ,  G06F11/3495 ,  G06F13/4022 ,  G06F13/4027

Abstract: A trace network for debugging integrated circuits is disclosed. At least one functional network includes a plurality of components interconnected by a number of network switches, implemented on at least one integrated circuit. A trace network is also implemented on the at least one integrated circuit, and includes a plurality of trace circuits configured to generate trace data based on transactions between ones of the plurality of components. The plurality of trace circuits are coupled to one another by a plurality of trace network switches. The trace circuits are configured to convey the generated trace data to an interface, via the trace network, without using the at least one functional network.

公开(公告)号：US20230334003A1

公开(公告)日：2023-10-19

申请号：US18306087

申请日：2023-04-24

Applicant: Apple Inc.

Inventor： Igor Tolchinsky ,  Charles J. Fleckenstein ,  Sagi Lahav ,  Lital Levy-Rubin

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4282 ,  G06F13/4027 ,  G06F2213/0038 ,  G06F2213/0042

Abstract: In an embodiment, an SOC includes a global communication fabric that includes multiple independent networks having different communication and coherency protocols, and a plurality of input-output (I/O) clusters that includes different sets of local functional circuits. A given I/O cluster may be coupled to one or more of the independent networks and may include a particular set of local functional circuits, a local fabric coupled to the particular set of local functional circuits, and an interface circuit coupled to the local fabric and configured to bridge transactions between the particular set of local functional circuits and the global communication fabric. The interface circuit may include a programmable hardware transaction generator circuit configured to generate a set of test transactions that simulate interactions between the particular set of local functional circuits and a particular one of the one or more independent networks.

公开(公告)号：US20220365896A1

公开(公告)日：2022-11-17

申请号：US17320169

申请日：2021-05-13

Applicant: Apple Inc.

Inventor： Igor Tolchinsky ,  Charles J. Fleckenstein ,  Sagi Lahav ,  Lital Levy-Rubin

IPC: G06F13/40 ,  G06F13/42

Abstract: In an embodiment, an SOC includes a global communication fabric that includes multiple independent networks having different communication and coherency protocols, and a plurality of input-output (I/O) clusters that includes different sets of local functional circuits. A given I/O cluster may be coupled to one or more of the independent networks and may include a particular set of local functional circuits, a local fabric coupled to the particular set of local functional circuits, and an interface circuit coupled to the local fabric and configured to bridge transactions between the particular set of local functional circuits and the global communication fabric. The interface circuit may include a programmable hardware transaction generator circuit configured to generate a set of test transactions that simulate interactions between the particular set of local functional circuits and a particular one of the one or more independent networks.

公开(公告)号：US11422184B1

公开(公告)日：2022-08-23

申请号：US17230443

申请日：2021-04-14

Applicant: Apple Inc.

Inventor： Charles J. Fleckenstein ,  Tal Lazmi ,  Ori Isachar

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/319

Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

公开(公告)号：US20250077384A1

公开(公告)日：2025-03-06

申请号：US18886122

申请日：2024-09-16

Applicant: Apple Inc.

Inventor： Charles J. Fleckenstein ,  Ori Isachar ,  Tal Lazmi

IPC: G06F11/34 ,  G01R31/317 ,  G06F11/30 ,  G06F13/40

Abstract: A trace network for debugging integrated circuits is disclosed. At least one functional network includes a plurality of components interconnected by a number of network switches, implemented on at least one integrated circuit. A trace network is also implemented on the at least one integrated circuit, and includes a plurality of trace circuits configured to generate trace data based on transactions between ones of the plurality of components. The plurality of trace circuits are coupled to one another by a plurality of trace network switches. The trace circuits are configured to convey the generated trace data to an interface, via the trace network, without using the at least one functional network.