公开(公告)号：US20240071773A1

公开(公告)日：2024-02-29

申请号：US18232916

申请日：2023-08-11

Applicant: Applied Materials, Inc.

Inventor： Lei Liao ,  Yichuan Ling ,  Zhiyu Huang ,  Hideyuki Kanzawa ,  Fenglin Wang ,  Rajesh Prasad ,  Yung-Chen Lin ,  Chi-I Lang ,  Ho-yung David Hwang ,  Lequn Liu

IPC: H01L21/3115 ,  H01L21/02

CPC classification number: H01L21/31155 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.

公开(公告)号：US20240332009A1

公开(公告)日：2024-10-03

申请号：US18616689

申请日：2024-03-26

Applicant: Applied Materials, Inc.

Inventor： Qixin Shen ,  Chuanxi Yang ,  Hang Yu ,  Deenesh Padhi ,  Prashanthi Para ,  Miguel S. Fung ,  Rajesh Prasad ,  Fenglin Wang ,  Shan Tang ,  Kyu-Ha Shim

IPC: H01L21/02 ,  H01L21/67

CPC classification number: H01L21/02321 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/67213

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon nitride on a semiconductor substrate. The layer of silicon nitride may be characterized by a first roughness. The methods may include performing a post-deposition treatment on the layer of silicon nitride. The methods may include reducing a roughness of the layer of silicon nitride such that the layer of silicon nitride may be characterized by a second roughness less than the first roughness.

公开(公告)号：US20250140566A1

公开(公告)日：2025-05-01

申请号：US18495493

申请日：2023-10-26

Applicant: Applied Materials, Inc.

Inventor： Aykut Aydin ,  Rajesh Prasad ,  Fenglin Wang ,  Rui Cheng ,  Karthik Janakiraman ,  Kyu-Ha Shim

IPC: H01L21/3115 ,  H01L21/033 ,  H01L21/311 ,  H10B12/00

Abstract: Thicker hardmasks are typically needed for etching deeper capacitor holes in a DRAM structure. Instead of increasing the hardmask thickness, hardmasks may instead be formed with an increased etch selectivity relative to the underlying semiconductor structure. For example, boron-based hardmasks may be formed that include a relatively high percentage of boron (e.g., greater than 90%). The etch selectivity of the hardmask may be improved by performing an ion implant process using different types of ions. The ion implant may take place before or after opening the hardmask with the pattern for the DRAM capacitor holes. Some designs may also tilt the semiconductor substrate relative to the ion implant process and rotate the substrate to provide greater ion penetration throughout a depth of the openings in the hardmask.

公开(公告)号：US20240379376A1

公开(公告)日：2024-11-14

申请号：US18314481

申请日：2023-05-09

Applicant: Applied Materials, Inc.

Inventor： Rajesh Prasad ,  Yung-Chen Lin ,  Zhiyu Huang ,  Fenglin Wang ,  Chi-I Lang ,  Hoyung David Hwang ,  Edwin A. Arevalo ,  KyuHa Shim

IPC: H01L21/3115 ,  C23C14/48 ,  G03F7/004 ,  G03F7/09 ,  G03F7/11

Abstract: Disclosed herein are approaches for reducing EUV dose during formation of a patterned metal oxide photoresist. In one approach, a method may include providing a stack of layers atop a substrate, the stack of layers comprising a film layer, and implanting the film layer with ions. The method may further include depositing a metal oxide photoresist atop the film layer, and patterning the metal oxide photoresist.