公开(公告)号：US20220107901A1

公开(公告)日：2022-04-07

申请号：US17064068

申请日：2020-10-06

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  James David DUNDAS ,  Chang Joo LEE ,  Muhammed Umar FAROOQ

IPC: G06F12/0897 ,  G06F12/0891 ,  G06F12/02

Abstract: First and second-level caches are provided. Cache control circuitry performs a first-level cache lookup of the first-level cache based on a lookup address, to determine whether the first-level cache stores valid cached data corresponding to the lookup address. When lookup hint information associated with the lookup address is available, the cache control circuitry determines based on the lookup hint information whether to activate or deactivate a second-level cache lookup of the second-level cache. The lookup hint information is indicative of whether the second-level cache is predicted to store valid cached data associated with the lookup address. When the second-level cache lookup is activated, the second-level cache lookup of the second-level cache is performed based on the lookup address to determine whether the second-level cache stores valid cached data corresponding to the lookup address.

公开(公告)号：US20230176979A1

公开(公告)日：2023-06-08

申请号：US17541007

申请日：2021-12-02

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Joseph Michael PUSDESRIS ,  . ABHISHEK RAJA ,  Karthik SUNDARAM ,  Anoop Ramachandra IYER ,  Michael Brian SCHINZLER ,  James David DUNDAS ,  Yasuo ISHII

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: An apparatus comprises memory management circuitry to perform a translation table walk for a target address of a memory access request and to signal a fault in response to the translation table walk identifying a fault condition for the target address, prefetch circuitry to generate a prefetch request to request prefetching of information associated with a prefetch target address to a cache; and faulting address prediction circuitry to predict whether the memory management circuitry would identify the fault condition for the prefetch target address if the translation table walk was performed by the memory management circuitry for the prefetch target address. In response to a prediction that the fault condition would be identified for the prefetch target address, the prefetch circuitry suppresses the prefetch request and the memory management circuitry prevents the translation table walk being performed for the prefetch target address of the prefetch request.

公开(公告)号：US20220100666A1

公开(公告)日：2022-03-31

申请号：US17036442

申请日：2020-09-29

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Chang Joo LEE ,  James David DUNDAS ,  Muhammed Umar FAROOQ

IPC: G06F12/0864 ,  G06F9/38 ,  G06F12/0891

Abstract: A data processing apparatus and a method are disclosed. The data processing apparatus comprising: a prediction cache to store a plurality of prediction entries, each defining an association between a prediction cache lookup address and a predicted behaviour; prediction circuitry to select a prediction entry based on a prediction cache lookup of the prediction cache based on a given prediction cache lookup address and to determine the predicted behaviour associated with the given prediction cache lookup address based on the selected prediction entry; and a candidate prediction buffer to store a plurality of candidate predictions each indicative of a candidate prediction entry to be selected for inclusion in a subsequent prediction cache lookup, wherein the candidate prediction entry is selected in response to a candidate prediction lookup based on a candidate lookup address different to a candidate prediction cache lookup address indicated as associated with a candidate predicted behaviour in the candidate prediction entry.

公开(公告)号：US20240095034A1

公开(公告)日：2024-03-21

申请号：US17949874

申请日：2022-09-21

Applicant: Arm Limited

Inventor： James David DUNDAS ,  Yasuo ISHII ,  Michael Brian SCHINZLER

IPC: G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3861

Abstract: A data processing apparatus includes control flow prediction circuitry that generates a control flow prediction in respect of a group of one or more instructions. Storage circuitry used by the control flow prediction circuitry stores data in association with groups of instructions used to generate the control flow prediction for each of the groups of instructions. Control flow prediction update circuitry inserts new data into the storage circuitry in association with a new group of one or more instructions in dependence on one or more conditions being met when a miss occurs for the group of one or more instructions in the storage circuitry.

公开(公告)号：US20240020237A1

公开(公告)日：2024-01-18

申请号：US17864625

申请日：2022-07-14

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Jungsoo KIM ,  James David DUNDAS ,  . ABHISHEK RAJA

IPC: G06F12/0897

CPC classification number: G06F12/0897 ,  G06F2212/60

Abstract: There is provided a data processing apparatus in which receive circuitry receives a result signal from a lower level cache and a higher level cache in respect of a first instruction block. The lower level cache and the higher level cache are arranged hierarchically and transmit circuitry transmits, to the higher level cache, a query for the result signal. In response to the result signal originating from the higher level cache containing requested data, the transmit circuitry transmits a further query to the higher level cache for a subsequent instruction block at an earlier time than the further query is transmitted to the higher level cache when the result signal containing the requested data originates from the lower level cache.

公开(公告)号：US20220107898A1

公开(公告)日：2022-04-07

申请号：US17060624

申请日：2020-10-01

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  James David DUNDAS ,  Chang Joo LEE ,  Muhammad Umar FAROOQ

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0873 ,  G06F12/121

Abstract: An apparatus comprises first-level and second-level set-associative caches each comprising the same number of sets of cache entries. Indexing circuitry generates, based on a lookup address, a set index identifying which set of the first-level set-associative cache or the second-level set-associative cache is a selected set of cache entries to be looked up for information associated with the lookup address. The indexing circuitry generates the set index using an indexing scheme which maps the lookup address to the same set index for both the first-level set-associative cache and the second-level set-associative cache. This can make migration of cached information between the cache levels more efficient, which can be particularly useful for caches with high access frequency, such as branch target buffers for a branch predictor.