公开(公告)号：US20240038297A1

公开(公告)日：2024-02-01

申请号：US17874611

申请日：2022-07-27

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L27/1104

Abstract: Various implementations described herein are related to a device having bitline drivers coupled to passgates of bitcells via bitlines and buried metal lines formed within a substrate including a buried enable signal line and a buried ground line coupled to ground connections of the bitline drivers. The buried enable signal line transfers a negative bias to a selected bitline of the bitlines via the buried ground line that is coupled to the ground connections of the bitline drivers so as to increase gate-source bias of the passgates of the selected bitcell to thereby enhance write capability of the selected bitcell.

公开(公告)号：US20230354571A1

公开(公告)日：2023-11-02

申请号：US18012917

申请日：2021-06-23

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Saurabh Pijuskumar Sinha ,  Brian Tracy Cline ,  Yew Keong Chong

IPC: H10B10/00

CPC classification number: H10B10/12

Abstract: Various implementations described herein refer to a device having a memory structure with a substrate. The device may have a signal wire buried or partially buried within at least one of the substrate and a dielectric for transmitting electrical signals. The device may be manufactured as a memory device having a memory cell structure with the signal wire buried or partially buried in the substrate.

公开(公告)号：US20230178538A1

公开(公告)日：2023-06-08

申请号：US18103313

申请日：2023-01-30

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

IPC: H01L27/02 ,  G06F30/31 ,  H01L21/768 ,  H01L23/535 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L27/0207 ,  G06F30/31 ,  H01L21/76898 ,  H01L23/535 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06544

Abstract: According to one implementation of the present disclosure, a method includes fabricating a memory macro unit; forming a through silicon via (TSV); and bonding the TSV at least partially through the fabricated memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

公开(公告)号：US11532353B2

公开(公告)日：2022-12-20

申请号：US17162532

申请日：2021-01-29

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Rahul Mathur ,  Andy Wangkun Chen

IPC: G11C11/41 ,  G11C11/419 ,  G11C11/418

Abstract: According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.

公开(公告)号：US20220391469A1

公开(公告)日：2022-12-08

申请号：US17339895

申请日：2021-06-04

Applicant: Arm Limited

Inventor： Supreet Jeloka ,  Mudit Bhargava ,  Saurabh Pijuskumar Sinha ,  Rahul Mathur

IPC: G06F17/16 ,  G06F9/30

Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.

公开(公告)号：US11468945B2

公开(公告)日：2022-10-11

申请号：US17071449

申请日：2020-10-15

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Joel Thornton Irby ,  Andy Wangkun Chen

IPC: G11C11/418 ,  G11C11/419

Abstract: A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.

公开(公告)号：US20220122655A1

公开(公告)日：2022-04-21

申请号：US17071449

申请日：2020-10-15

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Joel Thornton Irby ,  Andy Wangkun Chen

IPC: G11C11/418 ,  G11C11/419

Abstract: A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.

公开(公告)号：US10783957B1

公开(公告)日：2020-09-22

申请号：US16359758

申请日：2019-03-20

Applicant: Arm Limited

Inventor： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava

IPC: G11C7/00 ,  G11C11/419 ,  G11C16/08 ,  G11C16/12

Abstract: In a particular implementation, a method to perform a read operation on a voltage divider bit-cell having first and second transistors and first and second storage elements is disclosed. The method includes: providing a first voltage to a bit-line coupled to the second transistor of the voltage-divider bit-cell; providing a second voltage to a first word-line and providing an electrical grounding to a second word-line; where the first and second word-lines are coupled to the respective first and second resistive memory devices; and determining at least one of first and second data resistances in the respective first and second storage elements based on an output voltage on the bit-line.

公开(公告)号：US20200126619A1

公开(公告)日：2020-04-23

申请号：US16167822

申请日：2018-10-23

Applicant: Arm Limited

Inventor： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava ,  George McNeil Lattimore

IPC: G11C14/00 ,  G11C11/419 ,  G11C5/14 ,  G11C5/06

Abstract: Briefly, embodiments of claimed subject matter relate to backup of parameters, such as binary logic values, stored in nonvolatile memory, such as one or more SRAM cells. Binary logic values from a SRAM cell, for example, may be stored utilizing resistance states of a magnetic random-access memory (MRAM) element. Parameters stored in one or more MRAM elements may be restored to SRAM memory cells following a backup.

公开(公告)号：US20190325961A1

公开(公告)日：2019-10-24

申请号：US16201080

申请日：2018-11-27

Applicant: Arm Limited

Inventor： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava

IPC: G11C14/00 ,  G11C11/419 ,  G11C11/16 ,  G11C11/418

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.