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    Read and logic operation methods for voltage-divider bit-cell memory devices
    2.
    发明授权
    Read and logic operation methods for voltage-divider bit-cell memory devices 有权

    公开(公告)号：US10783957B1

    公开(公告)日：2020-09-22

    申请号：US16359758

    申请日：2019-03-20

    申请人： Arm Limited

    发明人： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava

    IPC分类号： G11C7/00 ,  G11C11/419 ,  G11C16/08 ,  G11C16/12

    摘要： In a particular implementation, a method to perform a read operation on a voltage divider bit-cell having first and second transistors and first and second storage elements is disclosed. The method includes: providing a first voltage to a bit-line coupled to the second transistor of the voltage-divider bit-cell; providing a second voltage to a first word-line and providing an electrical grounding to a second word-line; where the first and second word-lines are coupled to the respective first and second resistive memory devices; and determining at least one of first and second data resistances in the respective first and second storage elements based on an output voltage on the bit-line.

    D-MRAM devices and methods for replicating data and read and write operations
    7.
    发明授权
    D-MRAM devices and methods for replicating data and read and write operations 有权

    公开(公告)号：US10896730B1

    公开(公告)日：2021-01-19

    申请号：US16457808

    申请日：2019-06-28

    申请人： Arm Limited

    发明人： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava

    IPC分类号： G11C14/00 ,  G11C11/16 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/408

    摘要： In a particular implementation, a method of storing dynamic random-access memory (DRAM) data in respective magneto-electric magnetic tunnel junctions (ME-MTJ) of D-MRAM bit-cells of a D-MRAM bit-cell memory array, the method comprising: for each of the D-MRAM bit-cells: writing a first data value in a storage capacitor; and in a first cycle, providing a first voltage to a source line coupled to an ME-MTJ, wherein in response to the storage capacitor storing the first data value, the ME-MTJ is configured to store the first data value if the first voltage generates a voltage difference between first and second terminals of the ME-MTJ.

    Read and Logic Operation Methods for Voltage-Divider Bit-Cell Memory Devices
    9.
    发明申请
    Read and Logic Operation Methods for Voltage-Divider Bit-Cell Memory Devices 审中-公开

    公开(公告)号：US20200302996A1

    公开(公告)日：2020-09-24

    申请号：US16359758

    申请日：2019-03-20

    申请人： Arm Limited

    发明人： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava

    IPC分类号： G11C11/419 ,  G11C16/12 ,  G11C16/08

    摘要： In a particular implementation, a method to perform a read operation on a voltage divider bit-cell having first and second transistors and first and second storage elements is disclosed. The method includes: providing a first voltage to a bit-line coupled to the second transistor of the voltage-divider bit-cell; providing a second voltage to a first word-line and providing an electrical grounding to a second word-line; where the first and second word-lines are coupled to the respective first and second resistive memory devices; and determining at least one of first and second data resistances in the respective first and second storage elements based on an output voltage on the bit-line.