公开(公告)号：US20240028241A1

公开(公告)日：2024-01-25

申请号：US17871332

申请日：2022-07-22

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Steven Daniel MACLEAN ,  Nicholas Andrew PLANTE ,  Muhammad Umar FAROOQ ,  Michael Brian SCHINZLER ,  Nicholas Todd HUMPHRIES ,  Glen Andrew HARRIS

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0604 ,  G06F3/0673

Abstract: There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.

公开(公告)号：US20230418609A1

公开(公告)日：2023-12-28

申请号：US17851266

申请日：2022-06-28

Applicant: Arm Limited

Inventor： Joseph Michael PUSDESRIS ,  Alexander Cole SHULYAK ,  Yasuo ISHII ,  Houdhaifa BOUZGUARROU

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3861

Abstract: There is provided a data processing apparatus comprising history storage circuitry that stores sets of behaviours of helper instructions for a control flow instruction. Pointer storage circuitry stores pointers, each associated with one of the sets. The behaviours in the one of the sets are indexed according to one of the pointers associated with that one of the sets. Increment circuitry increments at least some of the pointers in response to an increment event and prediction circuitry determines a predicted behaviour of the control flow instruction using one of the sets of behaviours.

公开(公告)号：US20230195466A1

公开(公告)日：2023-06-22

申请号：US17554573

申请日：2021-12-17

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ ,  William Elton BURKY ,  Michael Brian SCHINZLER ,  Jason Lee SETTER ,  David Gum LIM

IPC: G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3867

Abstract: A data processing apparatus is provided that comprises rename circuitry for performing a register rename stage of a pipeline in respect of a stream of operations. Move elimination circuitry performs a move elimination operation on the stream of operations in which a move operation is eliminated and the register rename stage performs an adjustment of an identity of registers in the stream of operations to compensate for the move operation being eliminated and demotion circuitry reverses or inhibits the adjustment in response to one or more conditions being met.

公开(公告)号：US20200081719A1

公开(公告)日：2020-03-12

申请号：US16124247

申请日：2018-09-07

Applicant: Arm Limited

Inventor： William Elton BURKY ,  Glen Andrew HARRIS ,  Yasuo ISHII

IPC: G06F9/38 ,  G06F12/0875 ,  G06F12/0804 ,  G06F12/12

Abstract: A data processing apparatus is provided. It includes processing circuitry for speculatively executing a plurality of instructions. Storage circuitry stores a current state of the processing circuitry and a plurality of previous states of the processing circuitry. Execution of the plurality of instructions changes the current state of the processing circuitry. Flush circuitry replaces, in response to a miss-prediction, the current state of the processing circuitry with a replacement one of the plurality of previous states of the processing circuitry.

公开(公告)号：US20180121203A1

公开(公告)日：2018-05-03

申请号：US15335741

申请日：2016-10-27

Applicant: ARM LIMITED

Inventor： Yasuo ISHII ,  Michael FILIPPO ,  Muhammad Umar FAROOQ

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806

Abstract: An apparatus comprises a branch target buffer (BTB) to store predicted target addresses of branch instructions. In response to a fetch block address identifying a fetch block comprising two or more program instructions, the BTB performs a lookup to identify whether it stores one or more predicted target addresses for one or more branch instructions in the fetch block. When the BTB is identified in the lookup as storing predicted target addresses for more than one branch instruction in said fetch block, branch target selecting circuitry selects a next fetch block address from among the multiple predicted target addresses returned in the lookup. A shortcut path bypassing the branch target selecting circuitry is provided to forward a predicted target address identified in the lookup as the next fetch block address when a predetermined condition is satisfied.

公开(公告)号：US20220107901A1

公开(公告)日：2022-04-07

申请号：US17064068

申请日：2020-10-06

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  James David DUNDAS ,  Chang Joo LEE ,  Muhammed Umar FAROOQ

IPC: G06F12/0897 ,  G06F12/0891 ,  G06F12/02

Abstract: First and second-level caches are provided. Cache control circuitry performs a first-level cache lookup of the first-level cache based on a lookup address, to determine whether the first-level cache stores valid cached data corresponding to the lookup address. When lookup hint information associated with the lookup address is available, the cache control circuitry determines based on the lookup hint information whether to activate or deactivate a second-level cache lookup of the second-level cache. The lookup hint information is indicative of whether the second-level cache is predicted to store valid cached data associated with the lookup address. When the second-level cache lookup is activated, the second-level cache lookup of the second-level cache is performed based on the lookup address to determine whether the second-level cache stores valid cached data corresponding to the lookup address.

公开(公告)号：US20220107807A1

公开(公告)日：2022-04-07

申请号：US17064983

申请日：2020-10-07

Applicant: Arm Limited

Inventor： Michael Brian SCHINZLER ,  Yasuo ISHII ,  Muhammad Umar FAROOQ ,  Jason Lee SETTER

IPC: G06F9/30 ,  G06F12/0875 ,  G06F9/38

Abstract: An apparatus and method are provided for processing instructions fetched from memory. Decode circuitry is used to decode the fetched instructions in order to produce decoded instructions, and downstream circuitry then processes the decoded instructions in order to perform the operations specified by those decoded instructions. Dispatch circuitry is arranged to dispatch to the downstream circuitry up to N decoded instructions per dispatch cycle, and is arranged to determine, based on a given candidate sequence of decoded instructions being considered for dispatch in a given dispatch cycle, whether at least one resource conflict within the downstream circuitry would occur in the event that the given candidate sequence of decoded instructions is dispatched in the given dispatch cycle. The dispatch circuitry has resource checking circuitry arranged, by default, to perform a resource checking operation during the given dispatch cycle to generate, for the given candidate sequence of decoded instructions, resource conflict information used to determine whether a resource conflict would occur. Resource conflict information cache storage is provided to maintain, for one or more sequences of decoded instructions, associated resource conflict information. In the event that the given candidate sequence matches one of the sequences for which associated resource conflict information is cached, the dispatch circuitry employs the associated cached resource conflict information to determine whether a resource conflict would occur, instead of invoking the resource checking circuitry to perform the resource checking operation.

公开(公告)号：US20210026770A1

公开(公告)日：2021-01-28

申请号：US16520657

申请日：2019-07-24

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Matthew Andrew RAFACZ

IPC: G06F12/0815 ,  G06F12/0875 ,  G06F12/0808 ,  G06F12/1018 ,  G06F9/38

Abstract: A data processing apparatus is provided, which includes a cache to store operations produced by decoding instructions fetched from memory. The cache is indexed by virtual addresses of the instructions in the memory. Receiving circuitry receives an incoming invalidation request that references a physical address in the memory. Invalidation circuitry invalidates entries in the cache where the virtual address corresponds with the physical address. Coherency is thereby achieved when using a cache that is indexed using virtual addresses.

公开(公告)号：US20200150967A1

公开(公告)日：2020-05-14

申请号：US16185073

申请日：2018-11-09

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ ,  Chris ABERNATHY

IPC: G06F9/38 ,  G06F9/30

Abstract: Apparatus and a method of operating the same is disclosed. Instruction fetch circuitry is provided to fetch a block of instructions from memory and branch prediction circuitry to generate branch prediction indications for each branch instruction present in the block of instructions. The branch prediction circuitry is responsive to identification of a first conditional branch instruction in the block of instructions that is predicted to be taken to modify a branch prediction indication generated for the first conditional branch instruction to include a subsequent branch status indicator. When there is a subsequent branch instruction after the first conditional branch instruction in the block of instructions that is predicted to be taken the subsequent branch status indicator has a first value, and otherwise the subsequent branch status indicator has a second value. This supports improved handling of a misprediction as taken.

公开(公告)号：US20200081715A1

公开(公告)日：2020-03-12

申请号：US16124264

申请日：2018-09-07

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Chris ABERNATHY

IPC: G06F9/38 ,  G06F9/30

Abstract: A data processing apparatus is provided that includes a plurality of control flow execution circuits to simultaneously execute a first control flow instruction having a first type and a second control flow instruction having a second type from a plurality of instructions. A control flow prediction update circuit updates at most one of: a prediction of the first control flow instruction based on a result of the first control flow instruction, and a prediction of the second control flow instruction based on a result of the second control flow instruction.