公开(公告)号：US20200379842A1

公开(公告)日：2020-12-03

申请号：US16425377

申请日：2019-05-29

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Jason F. Ross

IPC: G06F11/10 ,  G11C11/56 ,  G11C11/16 ,  G06F1/3206 ,  G06F1/3287

Abstract: A disclosed apparatus and method reduce the likelihood of multiple bit single event upset (SEU) errors in space-deployed memory devices and memory macros, without requiring novel, specialized memory designs and without significant added cost or performance loss. For each memory, a bit selection layer effectively increases the mux of the memory bit table, thereby reducing the word size while increasing the word capacity, without changing the total memory capacity. As a result, the separation between the physical bit storage locations for each word is increased, thereby reducing the likelihood of multiple bit SEU errors. A buffer can be implemented if the memory lacks individual bit write control. The memory can be implemented in a core IC of an MCM-HIC, and the bit selection layer and/or buffer can be implemented in a chiplet or chiplets of the MCM-HIC.

公开(公告)号：US10135443B1

公开(公告)日：2018-11-20

申请号：US15668094

申请日：2017-08-03

Applicant: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.

Inventor： Jason F. Ross

IPC: H03K19/003 ,  H03K17/0814 ,  H03K19/177 ,  H03K19/00 ,  H03K19/0185

Abstract: An off chip driver circuit includes a bias circuit and a driver sub-cell circuit. The bias circuit and off chip driver sub-cell circuit are in electrical communication with each other. The bias circuit includes two serially aligned diodes which are in an off-state when the driver sub-cell is in a functional mode and which are in an on-state when the driver sub-cell is in a cold spare mode. The arrangement of the diodes enables the off chip driver circuit to handle similar voltage signals in both the functional mode and the cold spare mode.

公开(公告)号：US11379306B1

公开(公告)日：2022-07-05

申请号：US17388690

申请日：2021-07-29

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Jason F. Ross ,  John Foster ,  David M. Hutcheson

IPC: G06F11/00 ,  G06F11/10 ,  H03M13/29 ,  G11C11/4096 ,  G11C11/419 ,  G11C11/418 ,  G01R31/3177

Abstract: A method for radiation hardening synchronous Dynamic Random Access Memory (DRAM), where Error Detection And Correction (EDAC) is implemented on-chip. Each bank includes a plurality of interleaved single chip Static Random Access Memory (SRAM) cells with bit registers configured to interface with the interleaved SRAM cells. A first column multiplexer (MUX) configured to select which bit register is accessed. A second column multiplexer is configured to select an accessed byte with the WRITE burst or a READ burst from the selected bit registers of the first column multiplexer. EDAC logic is configured to check Error Correction Code (ECC) during a READ burst and generate ECC during an WRITE burst for SRAM writeback during a PRECHARGE command.

公开(公告)号：US10990471B2

公开(公告)日：2021-04-27

申请号：US16425377

申请日：2019-05-29

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Jason F. Ross

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/56 ,  G06F1/3287 ,  G11C11/16 ,  G06F1/3206

Abstract: A disclosed apparatus and method reduce the likelihood of multiple bit single event upset (SEU) errors in space-deployed memory devices and memory macros. For each memory, a bit selection layer effectively increases the mux of the memory bit table, thereby reducing the word size while increasing the word capacity, without changing the total memory capacity. As a result, the separation between the physical bit storage locations for each word is increased, thereby reducing the likelihood of multiple bit SEU errors. A buffer can be implemented if the memory lacks individual bit write control. The memory can be implemented in a core integrated circuit (IC) of an multi-chip module (MCM) hybrid integrated circuit (HIC), and the bit selection layer and/or buffer can be implemented in a chiplet or chiplets of the MCM-HIC.

公开(公告)号：US10348302B1

公开(公告)日：2019-07-09

申请号：US15994671

申请日：2018-05-31

Applicant: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.

Inventor： Jason F. Ross ,  Jamie A. Bernard ,  John T. Matta

IPC: H03K19/003 ,  H03K19/007 ,  H01L23/556 ,  H03K19/20

Abstract: A radiation-hardened electronic system is disclosed. The radiation-hardened electronic system includes a reconfigurable analog circuit block, a digital configuration logic circuit block, and a radiation-hardened isolation latch circuit connecting between the reconfigurable analog circuit block and the digital configuration logic circuit block. The reconfigurable analog circuit block includes multiple analog inputs and outputs. The digital configuration logic circuit block includes multiple digital inputs and outputs for controlling various functionalities of the reconfigurable analog circuit block via a set of configuration data. The radiation-hardened isolation latch circuit prevents the configuration data from entering the reconfigurable analog circuit block when the configuration data has been corrupted by a SEU.

公开(公告)号：US12080344B2

公开(公告)日：2024-09-03

申请号：US17552844

申请日：2021-12-16

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Jason F. Ross

IPC: G11C11/56 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C11/5692 ,  G11C17/16 ,  G11C17/18

Abstract: A multi-bit, asynchronous e-fuse macro, the macro comprising: the following inputs: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock; a plurality of e-fuse bits; a supply voltage configured to allow programming at least one of the e-fuse bits; at least one fuse output; and self-timing and control circuitry configured to perform signaling, wherein each of the inputs is in electrical communication with said e-fuse macro.

公开(公告)号：US20220392854A1

公开(公告)日：2022-12-08

申请号：US17742925

申请日：2022-05-12

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Jason F. Ross ,  Dale A Rickard

IPC: H01L23/00

Abstract: An integrated circuit (IC) implements a radiation tolerance limiting feature (RTLF) to ensure that the IC, as manufactured, will fail one or more applicable radiation tolerance tests, for example by reducing or eliminating a required voltage or blocking a required signal. As a result, the IC can be manufactured by any suitable IC foundry, and exported without restriction. The RTLF can include a leakage component, such as an oxide dielectric capacitor, a radiation-sensitive MOSFET or SCR, or a photocurrent generating component. The RTLF can include redundancy to ensure reliability. A plurality of RTLFs can be included to ensure failure of any desired combination of applicable radiation tolerance tests, such as total radiation dosage, linear energy transfer events, radiation dose rate, and single event upset. The RTLF can be obfuscated within the IC design. The RTLF can include a testing output to ensure its functionality.

公开(公告)号：US10854586B1

公开(公告)日：2020-12-01

申请号：US16422072

申请日：2019-05-24

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Lori D. Dennis ,  Jamie A. Bernard ,  Alan F. Dennis ,  Jane O. Gilliam ,  Jason F. Ross ,  Keith K. Sturcken ,  Dale A Rickard

IPC: G06N20/00 ,  G06F11/07 ,  H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L23/64 ,  H01L25/00 ,  H01L23/498 ,  H01L23/367

Abstract: A multi-chip module hybrid integrated circuit (MCM-HIC) provides cold spare support to an apparatus comprising a plurality of ICs and/or other circuits that are not cold spare compliant. At least one core IC and at least one cold spare chiplet are installed on an interconnecting substrate having a plurality of power zones to which power can be applied and withdrawn as needed. When powered, the cold spare chiplets serve as mediators and interfaces between the non cold spare compliant circuits. When the cold spare chiplets are at least partly unpowered, they protect all interconnected circuits, and ensure that interconnected circuits that remain powered are not hindered by unpowered interconnected circuits. Cold spare chiplets can extend across boundaries between power zones. External circuits can be exclusively interfaced to a subset of the power zones. Separate power circuits within a power zone can be sequenced during application and withdrawal of power.

公开(公告)号：US20200373286A1

公开(公告)日：2020-11-26

申请号：US16422072

申请日：2019-05-24

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Lori D. Dennis ,  Jamie A. Bernard ,  Alan F. Dennis ,  Jane O. Gilliam ,  Jason F. Ross ,  Keith K. Sturcken ,  Dale A Rickard

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L23/64 ,  H01L25/00 ,  H01L23/498 ,  H01L23/367

Abstract: A multi-chip module hybrid integrated circuit (MCM-HIC) provides cold spare support to an apparatus comprising a plurality of ICs and/or other circuits that are not cold spare compliant. At least one core IC and at least one cold spare chiplet are installed on an interconnecting substrate having a plurality of power zones to which power can be applied and withdrawn as needed. When powered, the cold spare chiplets serve as mediators and interfaces between the non cold spare compliant circuits. When the cold spare chiplets are at least partly unpowered, they protect all interconnected circuits, and ensure that interconnected circuits that remain powered are not hindered by unpowered interconnected circuits. Cold spare chiplets can extend across boundaries between power zones. External circuits can be exclusively interfaced to a subset of the power zones. Separate power circuits within a power zone can be sequenced during application and withdrawal of power.

公开(公告)号：US10714207B2

公开(公告)日：2020-07-14

申请号：US16146650

申请日：2018-09-28

Applicant: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.

Inventor： David D Moser ,  Michael J. Frack ,  Jason F. Ross ,  Kevin Linger

IPC: G11C8/00 ,  G11C29/32 ,  G11C7/22 ,  G11C7/10

Abstract: A scannable-latch random access memory (SLRAM) is disclosed. The SLRAM includes two rows of memory cells. The SLRAM includes a functional data input, a scan data input, a first and second functional data outputs, a scan data output, and a scan enable. The functional data input is connected to a first memory cell in a first and second rows of memory cells. The scan data input is connected to the first memory cell in the first or second row of memory cells. The first and second functional data outputs are connected to a last memory cell in the first and second row of memory cells, respectively. The scan data output is connected to the last memory cell in the first or second row of memory cells. The scan enable allows data to be output from the scan data output or the first and second functional data outputs.