公开(公告)号：US5261760A

公开(公告)日：1993-11-16

申请号：US873794

申请日：1992-04-27

申请人： Bertin Castonguay ,  Rejean Castonguay ,  Waguih Chikani ,  Jean Boucher ,  Pierre Michaud ,  Gilles Desharnais ,  Jacques Marc-Aurele ,  Elie Chiniara

发明人： Bertin Castonguay ,  Rejean Castonguay ,  Waguih Chikani ,  Jean Boucher ,  Pierre Michaud ,  Gilles Desharnais ,  Jacques Marc-Aurele ,  Elie Chiniara

IPC分类号： A01G9/28 ,  E01C11/22

CPC分类号： A01G1/08 ,  E01C11/221 ,  Y10S411/922

摘要： An improved curb section of precast concrete subdivided into modules by transverse grooves which give the appearance of shorter blocks and provide for fracturing the curb section at those locations. Each module of the curb section has a rearward T-shaped projection. L-shaped projection is formed at each end module of the curb section in proximity to the end face so that L-shaped projections of adjacent curb section form a projection equivalent to a T-shaped projection. T-shaped projections and an adjacent pair of L-shaped projections are anchored by sliding a channel-shaped anchor element which engages the projections and has a V-shaped lower end to penetrate the pavement or ground. The modules of the curb section can be of rectangular shape or tapered thereby defining rectilinear elongated curb sections or curved elongated curb sections which can be fastened adjacent to one another.

公开(公告)号：US20050149707A1

公开(公告)日：2005-07-07

申请号：US10743711

申请日：2003-12-24

申请人： Stephan Jourdan ,  Mark Davis ,  Pierre Michaud

发明人： Stephan Jourdan ,  Mark Davis ,  Pierre Michaud

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3848

摘要： Systems and methods of processing branch instructions provide for a bimodal predictor and a plurality of global predictors. The bimodal predictor is coupled to a prediction selector, where the bimodal predictor generates a bimodal prediction for branch instructions. The plurality of global predictors is coupled to the prediction selector, where each global predictor generates a corresponding global prediction for a branch instruction using different history or stew lengths. The prediction selector selects branch predictions from the bimodal prediction and the global predictions in order to arbitrate between predictors. The arbitration, update, and allocation schemes are designed to choose the most accurate predictor for each branch. Lower level predictors are used as filters to increase effective predictor capacity. Allocate and update schemes minimize aliasing between predictors. Branch predictors incorporating a plurality of global predictors in this fashion are more adaptive than conventional predictors with fixed branch history lengths and are able to achieve superior accuracy.

摘要翻译： 处理分支指令的系统和方法提供双峰预测器和多个全局预测器。 双模态预测器耦合到预测选择器，其中双模态预测器生成分支指令的双峰预测。 多个全局预测器被耦合到预测选择器，其中每个全局预测器使用不同的历史或炖长度来生成对于分支指令的相应的全局预测。 预测选择器从双模预测和全局预测中选择分支预测，以便在预测器之间进行仲裁。 仲裁，更新和分配方案旨在为每个分支选择最准确的预测器。 较低级别的预测变量被用作过滤器来增加有效的预测能力。 分配和更新方案使预测变量之间的混叠最小化。 以这种方式并入多个全局预测变量的分支预测器比具有固定分支历史长度的传统预测变量更适应，并且能够实现更高的精度。

公开(公告)号：US4155099A

公开(公告)日：1979-05-15

申请号：US831048

申请日：1977-09-06

申请人： Pierre Michaud

发明人： Pierre Michaud

IPC分类号： H04N5/073 ,  H04N5/04

CPC分类号： H04N5/073

摘要： The phase of local pulses at a line frequency F, produced in the control unit of a camera is synchronized both with the phase of reference pulses transmitted to the control unit from the camera and with that of incoming pulses received by the control unit from the exterior: in the control unit an oscillator of frequency NF (where N is large) synchronized with the incoming pulses sends, through an AND-gate, pulses to a first N-times divider formed of a counter; the AND-gate is controlled by a comparator circuit comparing the phase of the local pulses and the received reference pulses, the latter being formed of pulses which, in the camera, are in phase with the control pulses coming from the oscillator through a second N-times divider permanently supplied by the oscillator.

摘要翻译： 摄像机的控制单元产生的线频F处的本地脉冲相位与从摄像机发送到控制单元的参考脉冲的相位以及由控制单元从外部接收的输入脉冲的相位同步 ：在控制单元中，与输入脉冲同步的频率为NF（其中N大的）的振荡器通过与门将脉冲发送到由计数器形成的第一N倍分频器; 与门相比较，比较电路比较局部脉冲的相位和接收到的参考脉冲，后者由相机中的脉冲与来自振荡器的控制脉冲与第二N相同的脉冲形成 - 由振荡器永久提供的分频器。

公开(公告)号：US07243219B2

公开(公告)日：2007-07-10

申请号：US10743711

申请日：2003-12-24

申请人： Stephan J. Jourdan ,  Mark C. Davis ,  Pierre Michaud

发明人： Stephan J. Jourdan ,  Mark C. Davis ,  Pierre Michaud

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F15/00 ,  G06F9/44

CPC分类号： G06F9/3848

摘要： Systems and methods of processing branch instructions provide for a bimodal predictor and a plurality of global predictors. The bimodal predictor is coupled to a prediction selector, where the bimodal predictor generates a bimodal prediction for branch instructions. The plurality of global predictors is coupled to the prediction selector, where each global predictor generates a corresponding global prediction for a branch instruction using different history or stew lengths. The prediction selector selects branch predictions from the bimodal prediction and the global predictions in order to arbitrate between predictors. The arbitration, update, and allocation schemes are designed to choose the most accurate predictor for each branch. Lower level predictors are used as filters to increase effective predictor capacity. Allocate and update schemes minimize aliasing between predictors. Branch predictors incorporating a plurality of global predictors in this fashion are more adaptive than conventional predictors with fixed branch history lengths and are able to achieve superior accuracy.

摘要翻译： 处理分支指令的系统和方法提供双模态预测器和多个全局预测器。 双模态预测器耦合到预测选择器，其中双模态预测器生成分支指令的双峰预测。 多个全局预测器被耦合到预测选择器，其中每个全局预测器使用不同的历史或炖长度来生成对于分支指令的相应的全局预测。 预测选择器从双模预测和全局预测中选择分支预测，以便在预测器之间进行仲裁。 仲裁，更新和分配方案旨在为每个分支选择最准确的预测器。 较低级别的预测变量被用作过滤器来增加有效的预测能力。 分配和更新方案使预测变量之间的混叠最小化。 以这种方式并入多个全局预测变量的分支预测器比具有固定分支历史长度的传统预测变量更适应，并且能够实现更高的精度。

公开(公告)号：US20050138321A1

公开(公告)日：2005-06-23

申请号：US10743285

申请日：2003-12-23

申请人： Stephan Jourdan ,  Chris Yunker ,  Pierre Michaud

发明人： Stephan Jourdan ,  Chris Yunker ,  Pierre Michaud

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F12/0875 ,  G06F9/383 ,  G06F12/0864

摘要： Systems and methods of processing addresses provide for receiving a full linear address of an instruction and reducing a size of the full linear address to obtain a reduced linear address. A data block can be retrieved from a data array if the reduced linear address corresponds to a tag in a tag array, where the tag array is associated with the data array. The reduced linear address enables the tag array to either be smaller in size or achieve enhanced performance. The data array may be a prediction array of a branch predictor or a cache array of a cache.

摘要翻译： 处理地址的系统和方法提供用于接收指令的完整线性地址并减小全线性地址的大小以获得减小的线性地址。 如果减少的线性地址对应于标签阵列中的标签，其中标签阵列与数据阵列相关联，则可以从数据阵列检索数据块。 缩小的线性地址可使标签阵列的尺寸更小或实现增强的性能。 数据阵列可以是高速缓存的分支预测器或高速缓存阵列的预测阵列。

公开(公告)号：US07797683B2

公开(公告)日：2010-09-14

申请号：US10745527

申请日：2003-12-29

申请人： Per H. Hammarlund ,  Stephan J. Jourdan ,  Pierre Michaud ,  Alexandre J. Farcy ,  Morris Marden ,  Robert L. Hinton ,  Douglas M. Carmean

发明人： Per H. Hammarlund ,  Stephan J. Jourdan ,  Pierre Michaud ,  Alexandre J. Farcy ,  Morris Marden ,  Robert L. Hinton ,  Douglas M. Carmean

IPC分类号： G06F9/44

CPC分类号： G06F9/485 ,  G06F9/3851

摘要： Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.

摘要翻译： 管理线程的系统和方法提供支持具有多个同时物理线程的多个逻辑线程，其中逻辑线程的数量可以大于或小于物理线程的数量。 在一种方法中，多个逻辑线程中的每一个维持在等待状态，活动状态，排出状态和失速状态之一。 可以使用状态机和硬件定序器来基于触发事件来转换状态之间的逻辑线程，以及是否在逻辑线程中遇到可中断点。 逻辑线程被安排在物理线程上以满足例如优先级，性能或公平性目标。 也可以指定每个逻辑线程可用的资源，以满足这些目标和其他目标。 在一个示例中，单个逻辑线程可以推测使用多个物理线程，等待选择要提交哪个物理线程。

公开(公告)号：US07444457B2

公开(公告)日：2008-10-28

申请号：US10743285

申请日：2003-12-23

申请人： Stephan J. Jourdan ,  Chris E. Yunker ,  Pierre Michaud

发明人： Stephan J. Jourdan ,  Chris E. Yunker ,  Pierre Michaud

IPC分类号： G06F12/08

CPC分类号： G06F12/0875 ,  G06F9/383 ,  G06F12/0864

摘要： Systems and methods of processing addresses provide for receiving a full linear address of an instruction and reducing a size of the full linear address to obtain a reduced linear address. A data block can be retrieved from a data array if the reduced linear address corresponds to a tag in a tag array, where the tag array is associated with the data array. The reduced linear address enables the tag array to either be smaller in size or achieve enhanced performance. The data array may be a prediction array of a branch predictor or a cache array of a cache.

摘要翻译： 处理地址的系统和方法提供用于接收指令的完整线性地址并减小全线性地址的大小以获得减小的线性地址。 如果减少的线性地址对应于标签阵列中的标签，其中标签阵列与数据阵列相关联，则可以从数据阵列检索数据块。 缩小的线性地址可使标签阵列的尺寸更小或实现增强的性能。 数据阵列可以是高速缓存的分支预测器或高速缓存阵列的预测阵列。

公开(公告)号：US20050071614A1

公开(公告)日：2005-03-31

申请号：US10676310

申请日：2003-09-30

申请人： Stephan Jourdan ,  Per Hammarlund ,  Avinash Sodani ,  James Allen ,  Francis McKeen ,  Pierre Michaud

发明人： Stephan Jourdan ,  Per Hammarlund ,  Avinash Sodani ,  James Allen ,  Francis McKeen ,  Pierre Michaud

IPC分类号： G06F9/00 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/3842 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3861

摘要： A method and system for multiple branch paths in a microprocessor is described. The method includes assigning an identification number (ID) to each of a plurality of micro-operations (uops) to identify a branch path to which the uop belongs, determining whether one or more branches are predicted correctly, determining which of the one or more branch paths are dependent on a mispredicted branch, and determining whether one or more of the plurality of uops belong to a branch path that is dependent on a mispredicted branch based on their assigned IDs.

摘要翻译： 描述了微处理器中多个分支路径的方法和系统。 该方法包括：将识别号码（ID）分配给多个微操作（uop）中的每一个以识别该uop所属的分支路径，确定一个或多个分支是否被正确地预测，确定一个或多个 分支路径取决于错误预测的分支，并且基于其分配的ID来确定多个uops中的一个或多个是否属于依赖于错误预测的分支的分支路径。

公开(公告)号：US20050193278A1

公开(公告)日：2005-09-01

申请号：US10745527

申请日：2003-12-29

申请人： Per Hammarlund ,  Stephan Jourdan ,  Pierre Michaud ,  Alexandre Farcy ,  Morris Marden ,  Robert Hinton ,  Douglas Carmean

发明人： Per Hammarlund ,  Stephan Jourdan ,  Pierre Michaud ,  Alexandre Farcy ,  Morris Marden ,  Robert Hinton ,  Douglas Carmean

IPC分类号： G06F9/48 ,  G06F11/00

CPC分类号： G06F9/485 ,  G06F9/3851

摘要： Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.

摘要翻译： 管理线程的系统和方法提供支持具有多个同时物理线程的多个逻辑线程，其中逻辑线程的数量可以大于或小于物理线程的数量。 在一种方法中，多个逻辑线程中的每一个维持在等待状态，活动状态，排出状态和失速状态之一。 可以使用状态机和硬件定序器来基于触发事件来转换状态之间的逻辑线程，以及是否在逻辑线程中遇到可中断点。 逻辑线程被安排在物理线程上以满足例如优先级，性能或公平性目标。 也可以指定每个逻辑线程可用的资源，以满足这些目标和其他目标。 在一个示例中，单个逻辑线程可以推测使用多个物理线程，等待选择要提交哪个物理线程。

公开(公告)号：US4868663A

公开(公告)日：1989-09-19

申请号：US239422

申请日：1988-09-01

申请人： Jean L. Grimaldi ,  Raymond Dellion ,  Pierre Michaud

发明人： Jean L. Grimaldi ,  Raymond Dellion ,  Pierre Michaud

IPC分类号： H04N1/113 ,  H04N9/11

CPC分类号： H04N9/11 ,  H04N1/113

摘要： The invention relates to a device for scanning still images as applicable in particular to high-definition television (HDTV) systems. In accordance with customary practice, the entire still image is converted by an optical system having an oscillating mirror to an image which passes in front of a linear sensor having photosensitive elements. Diffusion of the optical system causes detachment of dark areas which are adjacent to bright areas. In order to prevent this detachment, the movement of a shutter provided with slits is synchronized with the movement of the mirror so as to occult part of the image which passes in front of the sensor, thus leaving only the zone located at the level of the sensor.

摘要翻译： 本发明涉及一种特别适用于高分辨率电视（HDTV）系统的扫描静止图像的装置。 根据惯例，通过具有振动反射镜的光学系统将整个静止图像转换成通过具有感光元件的线性传感器前方的图像。 光学系统的扩散导致与明亮区域相邻的暗区域的分离。 为了防止这种脱离，设置有狭缝的活门的移动与镜的运动同步，以隐藏通过传感器前方的图像的一部分，因此仅留下位于 传感器。