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    Compact non-volatile memory cell and array system
    1.
    发明申请
    Compact non-volatile memory cell and array system 有权
    紧凑型非易失性存储单元和阵列系统

    公开(公告)号：US20060209597A1

    公开(公告)日：2006-09-21

    申请号：US11084213

    申请日：2005-03-17

    Applicant: Bin Wang ,  Christopher Diorio ,  Todd Humes

    Inventor： Bin Wang ,  Christopher Diorio ,  Todd Humes

    IPC: G11C11/34

    CPC classification number: G11C16/24

    Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, a programming element, and a logic storage element. During a programming or erase mode, the floating gate of each cell is charged to a predetermined level. At the beginning of a read mode, all storage elements are pre-charged to a high supply voltage level. Following the pre-charge, selected cells are read to determine stored bit values. A charge status of the floating gate of each cell determines whether the storage element is turned on and the pre-charge voltage is pulled down corresponding to a bit value.

    Abstract translation: NVM阵列包括包括浮动栅极，编程元件和逻辑存储元件的NVM单元的行和列。 在编程或擦除模式期间，每个单元的浮置栅极被充电到预定的电平。 在读取模式开始时，所有存储元件都被预先充电到高电源电压。 在预充电之后，读取所选择的单元以确定存储的位值。 每个单元的浮动栅极的充电状态确定存储元件是否导通，并且预充电电压相应于位值被下拉。

    System and methods for retention-enhanced programmable shared gate logic circuit
    2.
    发明申请
    System and methods for retention-enhanced programmable shared gate logic circuit 审中-公开
    保持增强可编程共享门逻辑电路的系统和方法

    公开(公告)号：US20060226489A1

    公开(公告)日：2006-10-12

    申请号：US11095938

    申请日：2005-03-30

    Applicant: Bin Wang ,  Todd Humes

    Inventor： Bin Wang ,  Todd Humes

    IPC: H01L29/76

    CPC classification number: H01L27/115 ,  G11C16/0441 ,  G11C16/045 ,  H01L27/11521 ,  H01L27/11558

    Abstract: Retention-enhanced, programmable, shared floating gate logic circuits are employed as NVM cells. In one embodiment, the NVM cell is formed by a dual transistor logic gate circuit with a shared floating gate. The logic circuit is an inverter. The shared floating gate is doped partially or completely with p-type impurities to enhance retention. A charge adjustment circuit is arranged to inject and remove electrons to and from the shared floating gate determining the output of the logic gate circuit when supply voltage is applied to the logic gate circuit. In another embodiment, four transistors are employed to form another logic circuit such as a NOR gate or a NAND gate.

    Abstract translation: 采用保持增强型可编程共享浮栅逻辑电路作为NVM单元。 在一个实施例中，NVM单元由具有共享浮动栅极的双晶体管逻辑门电路形成。 逻辑电路是一个逆变器。 共享浮栅部分或完全掺杂有p型杂质以增强保留性。 电荷调整电路被布置成当向逻辑门电路施加电源电压时，向共享浮置栅极注入和去除电子，以确定逻辑门电路的输出。 在另一个实施例中，采用四个晶体管来形成诸如或非门或与非门的另一个逻辑电路。

    Magnet
    3.
    外观设计
    Magnet 有权

    公开(公告)号：USD1039353S1

    公开(公告)日：2024-08-20

    申请号：US29782500

    申请日：2021-05-07

    Applicant: Yang He ,  Bin Wang

    Designer： Yang He ,  Bin Wang

    Abstract: FIG. 1 is a perspective view of a magnet showing our new design;
    FIG. 2 is a front elevation view thereof;
    FIG. 3 is a rear elevation view thereof;
    FIG. 4 is a left side elevation view thereof;
    FIG. 5 is a right side elevation view thereof;
    FIG. 6 is a top plan view thereof; and,
    FIG. 7 is a bottom plan view thereof.
    The broken line showing of a magnet is for the purpose of illustrating portions of the article and forms no part of the claimed design.

    Hair clipper
    4.
    外观设计
    Hair clipper 有权

    公开(公告)号：USD972780S1

    公开(公告)日：2022-12-13

    申请号：US29828970

    申请日：2022-03-02

    Applicant: Bin Wang

    Designer： Bin Wang

    Hair trimmer
    5.
    外观设计
    Hair trimmer 有权

    公开(公告)号：USD972779S1

    公开(公告)日：2022-12-13

    申请号：US29828969

    申请日：2022-03-02

    Applicant: Bin Wang

    Designer： Bin Wang

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