公开(公告)号：US20160126289A1

公开(公告)日：2016-05-05

申请号：US14795882

申请日：2015-07-09

Applicant: Choong-jae LEE ,  Hong-kook MIN ,  Bo-young SEO ,  Aliaksei IVANIUKOVICH ,  Yong-kyu LEE

Inventor： Choong-jae LEE ,  Hong-kook MIN ,  Bo-young SEO ,  Aliaksei IVANIUKOVICH ,  Yong-kyu LEE

IPC: H01L27/22 ,  H01L29/08 ,  H01L29/78 ,  H01L43/02

CPC classification number: H01L27/228 ,  H01L29/1045 ,  H01L29/7833 ,  H01L29/7835 ,  H01L43/08

Abstract: A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.

Abstract translation: 半导体器件包括能够以低功率执行多个功能的磁阻器件。 半导体器件包括单元晶体管，其中第一杂质区域和第二杂质区域分别布置在沟道方向上的沟道区域的两侧，连接到单元晶体管的第一杂质区域的源极线和磁体 电阻器件连接到单元晶体管的第二杂质区域。 相对于形状和杂质浓度分布中的至少一种，第一杂质区域和第二杂质区域围绕单元晶体管的沟道方向的中心不对称。

公开(公告)号：US20170053688A1

公开(公告)日：2017-02-23

申请号：US15153866

申请日：2016-05-13

Applicant: Bo-young SEO ,  Yong-seok CHUNG ,  Gwan-hyeob KOH ,  Yong-kyu LEE

Inventor： Bo-young SEO ,  Yong-seok CHUNG ,  Gwan-hyeob KOH ,  Yong-kyu LEE

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  H01L27/228 ,  H01L43/08

Abstract: A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.

Abstract translation: 电阻式存储装置包括具有多个存储单元的存储单元阵列和第一接地开关。 多个存储单元被布置成多行和多列，并且多个存储单元的第一列中的每个存储单元连接在第一位线和第一源极线之间。 第一接地开关与第一源极线并联连接，并且第一接地开关被配置为选择性地提供从第一位线到接地的第一电流路径，通过多个存储单元的第一列中的选定存储单元， 第一个源行，当前路径仅遍历第一个源行的一部分。

公开(公告)号：US20170047507A1

公开(公告)日：2017-02-16

申请号：US15093006

申请日：2016-04-07

Applicant: Bo-young SEO ,  Yong-kyu LEE

Inventor： Bo-young SEO ,  Yong-kyu LEE

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08

Abstract: A magnetic random-access memory (MRAM) device and a semiconductor package include a magnetic shielding layer that may suppress at least one of magnetic orientation errors and deterioration of magnetic tunnel junction (MTJ) structures due to external magnetic fields. A semiconductor device includes: a MRAM chip including a MRAM; and a magnetic shielding layer including an upper shielding layer and a via shielding layer. The upper shielding layer is on a top surface of the MRAM chip, and the via shielding layer extends from the upper shielding layer and passes through the MRAM chip.

Abstract translation: 磁性随机存取存储器（MRAM）器件和半导体封装包括磁屏蔽层，其可以抑制由于外部磁场而引起的磁性取向误差和磁性隧道结（MTJ）结构的劣化中的至少一种。 半导体器件包括：包括MRAM的MRAM芯片; 以及包括上屏蔽层和通孔屏蔽层的磁屏蔽层。 上屏蔽层位于MRAM芯片的顶表面上，并且通孔屏蔽层从上屏蔽层延伸并通过MRAM芯片。