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    Aggregated page fault signaling and handline
    2.
    发明授权
    Aggregated page fault signaling and handline 有权

    公开(公告)号：US09891980B2

    公开(公告)日：2018-02-13

    申请号：US13977106

    申请日：2011-12-29

    申请人： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

    发明人： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

    IPC分类号： G06F11/07 ,  G06F9/30 ,  G06F12/08

    CPC分类号： G06F11/0784 ,  G06F9/30036 ,  G06F9/30043 ,  G06F12/08

    摘要： A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

    AGGREGATED PAGE FAULT SIGNALING AND HANDLINE
    3.
    发明申请
    AGGREGATED PAGE FAULT SIGNALING AND HANDLINE 有权
    聚合页错误信号和手段

    公开(公告)号：US20140304559A1

    公开(公告)日：2014-10-09

    申请号：US13977106

    申请日：2011-12-29

    申请人： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

    发明人： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

    IPC分类号： G06F11/07

    CPC分类号： G06F11/0784 ,  G06F9/30036 ,  G06F9/30043 ,  G06F12/08

    摘要： A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

    摘要翻译： 一方面的处理器包括处理指示多个存储器地址的多存储器地址指令的指令流水线。 处理器还包括与指令流水线相结合的多页故障聚合逻辑。 多页面故障聚合逻辑是针对与指令的多个存储器地址之一相关联的多个页面故障聚合页面故障信息。 多页面故障聚合逻辑是为页面故障通信接口提供聚合页面故障信息。 还公开了其他处理器，装置，方法和系统。

    SYNCHRONOUS SOFTWARE INTERFACE FOR AN ACCELERATED COMPUTE ENGINE
    10.
    发明申请
    SYNCHRONOUS SOFTWARE INTERFACE FOR AN ACCELERATED COMPUTE ENGINE 审中-公开
    用于加速计算机发动机的同步软件接口

    公开(公告)号：US20130268804A1

    公开(公告)日：2013-10-10

    申请号：US13994371

    申请日：2011-12-30

    申请人： Ronny Ronen ,  Boris Ginzburg ,  Eliezer Weissmann

    发明人： Ronny Ronen ,  Boris Ginzburg ,  Eliezer Weissmann

    IPC分类号： G06F9/54 ,  G06F11/14

    CPC分类号： G06F11/0724 ,  G06F9/3881 ,  G06F9/4484 ,  G06F9/54 ,  G06F9/542 ,  G06F11/0793 ,  G06F11/1474

    摘要： Some implementations disclosed herein provide techniques and arrangements for a synchronous software interface for a specialized logic engine. The synchronous software interface may receive, from a first core of a plurality of cores, a control block including a transaction for execution by the specialized logic engine. The synchronous software interface may send the control block to the specialized logic engine and wait to receive a confirmation from the specialized logic engine that the transaction was successfully executed.

    摘要翻译： 本文中公开的一些实施例提供了用于专用逻辑引擎的同步软件接口的技术和布置。 同步软件接口可以从多个核心的第一核心接收包括专用逻辑引擎执行的事务的控制块。 同步软件接口可以将控制块发送到专用逻辑引擎，并等待从专门的逻辑引擎接收事务成功执行的确认。