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    Method and system for managing congestion in a network
    2.
    发明授权
    Method and system for managing congestion in a network 失效
    管理网络拥塞的方法和系统

    公开(公告)号：US06657962B1

    公开(公告)日：2003-12-02

    申请号：US09546651

    申请日：2000-04-10

    申请人： Peter Irma August Barri ,  Brian Mitchell Bass ,  Jean Louis Calvignac ,  Ivan Oscar Clemminck ,  Marco C. Heddes ,  Clark Debs Jeffries ,  Michael Steven Siegel ,  Fabrice Jean Verplanken ,  Miroslav Vrana

    发明人： Peter Irma August Barri ,  Brian Mitchell Bass ,  Jean Louis Calvignac ,  Ivan Oscar Clemminck ,  Marco C. Heddes ,  Clark Debs Jeffries ,  Michael Steven Siegel ,  Fabrice Jean Verplanken ,  Miroslav Vrana

    IPC分类号： H04L1256

    CPC分类号： H04L47/2441 ,  H04L47/10 ,  H04L47/12 ,  H04L47/30 ,  H04L47/32 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/50 ,  H04L49/90

    摘要： A system for minimizing congestion in a communication system is disclosed. The system comprises at least one ingress system for providing data. The ingress system includes a first free queue and a first flow queue. The system also includes a first congestion adjustment module for receiving congestion indications from the free queue and the flow queue. The first congestion adjustment module generates end stores transmit probabilities and performs per packet flow control actions. The system further includes a switch fabric for receiving data from the ingress system and for providing a congestion indication to the ingress system. The system further includes at least one egress system for receiving the data from the switch fabric. The egress system includes a second free queue and a second flow queue. The system also includes a second congestion adjustment module for receiving congestion indications from the second free queue and the second flow queue. The second congestion adjustment module generates and stores transmit probabilities and performs per packet flow control actions. Finally, the system includes a scheduler for determining the order and timing of transmission of packets out the egress system and to another node or destination. A method and system in accordance with the present invention provides for a unified method and system for logical connection of congestion with the appropriate flow control responses. The method and system utilizes congestion indicators within the ingress system, egress system, and the switch fabric in conjunction with a coarse adjustment system and fine adjustment system within the ingress device and the egress device to intelligently manage the system.

    摘要翻译： 公开了一种用于最小化通信系统中的拥塞的系统。 该系统包括用于提供数据的至少一个入口系统。 入口系统包括第一空闲队列和第一流队列。 该系统还包括用于从空闲队列和流队列接收拥塞指示的第一拥塞调整模块。 第一拥塞调整模块生成终端存储发送概率并执行每个分组流控制动作。 该系统还包括用于从入口系统接收数据并向入口系统提供拥塞指示的交换结构。 该系统还包括用于从交换结构接收数据的至少一个出口系统。 出口系统包括第二空闲队列和第二流队列。 该系统还包括第二拥塞调整模块，用于从第二空闲队列和第二流队列接收拥塞指示。 第二拥塞调整模块生成并存储发送概率，并执行每个分组流控制动作。 最后，该系统包括一个调度器，用于确定出口系统和另一个节点或目的地的分组传输的顺序和定时。 根据本发明的方法和系统提供了用于将拥塞与适当流控制响应逻辑连接的统一方法和系统。 该方法和系统利用入口系统，出口系统和交换结构中的拥塞指示符与入口设备和出口设备内的粗调系统和精细调整系统结合，智能地管理系统。

    Network processor/software control architecture
    3.
    发明授权
    Network processor/software control architecture 失效
    网络处理器/软件控制架构

    公开(公告)号：US06898179B1

    公开(公告)日：2005-05-24

    申请号：US09544896

    申请日：2000-04-07

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Mark Anthony Rinaldi ,  Michael Steven Siegel ,  Colin Beaton Verrilli ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Mark Anthony Rinaldi ,  Michael Steven Siegel ,  Colin Beaton Verrilli ,  Fabrice Jean Verplanken

    IPC分类号： G06F11/00 ,  H04B7/216 ,  H04L1/16 ,  H04L12/26

    CPC分类号： G06F15/17

    摘要： The transport protocol for communicating between general purpose processors acting as contact points and network processors in a packet processing environment such as Ethernet is provided. In such an environment, there is at least one single control point processor (CP) and a plurality of network processors (NP), sometimes referred to as blades. A typical system could contain two to sixteen network processors, and each network processor connects to a plurality of devices which communicate with each other over a network transport, such as Ethernet. The CP typically controls the functionality and the functioning of the network processors to function in a way that connects one end user with another, whether or not the end user is on the same network processor or a different network processor. There are three types of communication provided; first, there is communication generally referred to as control services and normally there will be only one pico processor which operates as a GCH (guided cell handler) and only one that operates as a guided tree handler (GTH). A path is provided for the controls to the GCH and the GTH commands, and a separate path is provided for the data frames between the GDH's (general data handler) and the CP.

    摘要翻译： 提供了用于在诸如以太网的分组处理环境中用作接触点的通用处理器和网络处理器之间进行通信的传输协议。 在这样的环境中，存在至少一个单个控制点处理器（CP）和多个网络处理器（NP），有时称为刀片。 典型的系统可以包含两到十六个网络处理器，并且每个网络处理器连接到通过诸如以太网的网络传输彼此通信的多个设备。 CP通常控制网络处理器的功能和功能，以使终端用户与另一终端用户相连的方式起作用，无论终端用户是否在同一个网络处理器或不同的网络处理器上。 提供三种通讯方式; 首先，通常被称为控制服务的通信，并且通常将只有一个微微处理器作为GCH（引导的单元处理器）操作，并且只有一个作为引导树处理器（GTH）操作。 为GCH和GTH命令的控制提供路径，并为GDH（通用数据处理程序）和CP之间的数据帧提供单独的路径。

    Mixed queue scheduler
    5.
    发明授权
    Mixed queue scheduler 失效
    混合队列调度程序

    公开(公告)号：US06728253B1

    公开(公告)日：2004-04-27

    申请号：US09405691

    申请日：1999-09-24

    申请人： Clark Debs Jeffries ,  Marco C. Heddes ,  Mark Anthony Rinaldi ,  Michael Steven Siegel

    发明人： Clark Debs Jeffries ,  Marco C. Heddes ,  Mark Anthony Rinaldi ,  Michael Steven Siegel

    IPC分类号： H04L1256

    CPC分类号： H04L47/50 ,  H04L2012/5682

    摘要： A method and system are disclosed for allocating data input bandwidth from a source link to a plurality of N data queues each having a variable occupancy value, Qi(t), and a constant decrement rate, Di, where i designated the ith queue among the N queues. First, a threshold occupancy value, T, is designated for the N queues. During each time step of a repeating time interval, &Dgr;t, the occupancy value, Qi, is compared with T. In response to each and every of said N data queues having occupancy values exceeding T, pausing data transmission from the source link to the N data queues, such that overflow within the data queues is minimized. In response to at least one of the N data queues having an occupancy value less than or equal to T, selecting one among the N data queues to be incremented, and incrementing the selected data queue, such that underflow of the selected queue is minimized. In the context of scheduling one cell per time step, the value of T is one. Furthermore, the method of the present invention guarantees that output port occupancy shall never, in that context, exceed two cells.

    摘要翻译： 公开了一种用于将数据输入带宽从源链路分配给多个N个数据队列的方法和系统，每个N个数据队列具有可变占用值Qi（t）和常数递减率Di，其中i指定i < 排队N队列。 首先，为N个队列指定阈值占有率T。 在重复时间间隔的每个时间步长，Deltat，占用值Qi与T进行比较。响应于具有超过T的占用值的所述N个数据队列中的每一个，暂停从源链路到N的数据传输 数据队列，使数据队列中的溢出最小化。 响应于具有小于或等于T的占用值的N个数据队列中的至少一个，选择要增加的N个数据队列中的一个，并增加所选择的数据队列，使得所选队列的下溢最小化。 在每个时间步长调度一个单元格的上下文中，T的值为1。 此外，本发明的方法保证输出端口占用在这方面永远不超过两个小区。

    Full match (FM) search algorithm implementation for a network processor
    6.
    发明授权
    Full match (FM) search algorithm implementation for a network processor 失效
    网络处理器的完全匹配（FM）搜索算法实现

    公开(公告)号：US07139753B2

    公开(公告)日：2006-11-21

    申请号：US10650327

    申请日：2003-08-28

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： G06F7/00 ,  H04L12/28

    CPC分类号： H04L45/742 ,  H04L45/7453 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99937 ,  Y10S707/99943 ,  Y10S707/99945

    摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.

    摘要翻译： 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。 用于存储散列键和树中相关信息的数据结构称为叶。 每个叶对应于与输入键完全匹配的单个键。 叶包含关键以及其他信息。 叶片的长度是可编程的，密钥的长度也是可编程的。 叶存储在随机存取存储器中，并被实现为单个存储器条目。 如果键位于直接表中，则称为直接叶。

    Method and apparatus for processing frame classification information between network processors
    7.
    发明授权
    Method and apparatus for processing frame classification information between network processors 失效
    用于处理网络处理器之间帧分类信息的方法和装置

    公开(公告)号：US07106730B1

    公开(公告)日：2006-09-12

    申请号：US09546833

    申请日：2000-04-11

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/56

    CPC分类号： H04L49/30

    摘要： A network device including an ingress processor and egress processor which receives frames of data over the network on an input port, and transfers it to an appropriate output port. The received frame is processed by an ingress processor which prepares an intra-switch frame for delivery to an egress processor serving a relevant output port of the switch. The intra-switch frame includes a frame header having parameters which have been determined by the ingress processor, as well as data indicating an address for the egress processor for beginning processing of the frame. By identifying to the egress processor processing which has already taken place, the egress processor is relieved of any redundant processing of the frame. The egress processor provides a hardware frame classifier which decodes the information contained in the intra-frame header to derive parameters which have been previously computed as well as a starting address for the egress processor. By reducing the amount of redundant processing of the egress processor, total device throughput delay is reduced.

    摘要翻译： 一种网络设备，包括入口处理器和出口处理器，其在输入端口上通过网络接收数据帧，并将其传送到适当的输出端口。 接收到的帧由入口处理器处理，入口处理器准备一个内部交换帧，用于传送到服务于交换机的相关输出端口的出口处理器。 帧内切换帧包括具有由入口处理器确定的参数的帧报头，以及指示用于开始处理该帧的出口处理器的地址的数据。 通过识别已经发生的出口处理器处理，出口处理器免除了帧的任何冗余处理。 出口处理器提供硬件帧分类器，其对包含在帧内报头中的信息进行解码以导出先前已经计算的参数以及出口处理器的起始地址。 通过减少出口处理器的冗余处理量，减少了总设备吞吐量延迟。

    Method and system for network processor scheduling outputs based on multiple calendars
    8.
    发明授权
    Method and system for network processor scheduling outputs based on multiple calendars 失效
    基于多个日历的网络处理器调度输出的方法和系统

    公开(公告)号：US06862292B1

    公开(公告)日：2005-03-01

    申请号：US09548910

    申请日：2000-04-13

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04L12/28

    CPC分类号： H04Q11/0478 ,  H04L47/2425 ,  H04L47/50 ,  H04L47/52 ,  H04L47/627 ,  H04L2012/5636 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5681

    摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.

    摘要翻译： 一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。 本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。 优选实施例中的优先级包括低延迟服务，最小带宽，加权公平排队以及用于在较长时间内防止用户继续超过其服务水平的系统。 本发明包括具有不同服务速率的多个日历，以允许用户选择他所期望的服务速率。 如果客户选择了高带宽的服务，客户将被包含在比客户选择较低带宽的情况下更频繁地服务的日历。