公开(公告)号：US06730975B2

公开(公告)日：2004-05-04

申请号：US10207169

申请日：2002-07-30

申请人： Byung-Jun Park ,  Kyu-Hyun Lee

发明人： Byung-Jun Park ,  Kyu-Hyun Lee

IPC分类号： H01L31119

CPC分类号： H01L27/10855 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/10885 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A DRAM device in which a portion of bit lines has enlarged width portions at a portion of a peripheral/core area to be connected with upper layered circuit wiring through metal contacts, includes spacers formed of a layer of material having an etch selectivity with respect to a bit line interlayer insulating layer deposited after said bit lines are formed, and disposed on sides of an upper surface of each said enlarged width portion to protect sides of said enlarged width portions; an interlayer insulating layer and at least a portion of an etch stop layer disposed between said bit lines and transistors of a substrate; and metal contact pads formed along with bit line contact plugs to pass through said interlayer insulating layer and said etch stop layer.

摘要翻译： 一种DRAM器件，其中位线的一部分在通过金属触点与上部分层电路布线连接的外围/核心区域的一部分处具有扩大的宽度部分，包括由相对于 在所述位线形成之后沉积的位线层间绝缘层，并且设置在每个所述扩大宽度部分的上表面的侧面上，以保护所述扩大宽度部分的侧面; 层间绝缘层和设置在基板的所述位线和晶体管之间的蚀刻停止层的至少一部分; 以及与位线接触插塞一起形成的金属接触垫，以穿过所述层间绝缘层和所述蚀刻停止层。

公开(公告)号：US06451651B1

公开(公告)日：2002-09-17

申请号：US09931861

申请日：2001-08-20

申请人： Byung-Jun Park ,  Kyu-Hyun Lee

发明人： Byung-Jun Park ,  Kyu-Hyun Lee

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/10885 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a DRAM device comprises forming a bit line interlayer insulating layer over a substrate over which a bit line pattern is formed; planarizing the bit line interlayer insulating layer; forming enlarged grooves exposing a conductive layer of the bit line pattern; forming bit lines; forming a silicon nitride layer over the substrate; forming a silicon nitride pattern having silicon nitride spacers formed on side walls of the enlarged grooves positioned on the conductive layer; forming the bit lines at the enlarged width portions of the bit line pattern; forming storage node contacts, storage nodes, a dielectric layer, and plate electrodes at a cell area; forming a wiring interlayer insulating layer on the substrate; forming metal contact holes; and forming plugs filling the metal contact holes.

摘要翻译： 制造DRAM器件的方法包括在衬底上形成位线层间绝缘层，在其上形成位线图案; 平面化位线层间绝缘层; 形成暴露位线图案的导电层的扩大凹槽; 形成位线; 在衬底上形成氮化硅层; 形成具有形成在位于所述导电层上的所述扩大凹槽的侧壁上的氮化硅间隔物的氮化硅图案; 在位线图形的放大宽度部分形成位线; 在单元区域形成存储节点触点，存储节点，电介质层和平板电极; 在基板上形成布线层间绝缘层; 形成金属接触孔; 并形成填充金属接触孔的塞子。

公开(公告)号：US07153727B2

公开(公告)日：2006-12-26

申请号：US10719624

申请日：2003-11-20

申请人： Ju-Yong Lee ,  Kyu-Hyun Lee

发明人： Ju-Yong Lee ,  Kyu-Hyun Lee

IPC分类号： H01L21/82

CPC分类号： H01L27/10855 ,  H01L21/31144 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.

摘要翻译： 本文公开了一种半导体器件及其制造方法，其随着尺寸设计限制的降低而增加这些器件的可靠性。 通常，在基板上形成包括导电膜图案和第二绝缘膜图案的第一绝缘膜和布线。 在布线的侧壁上形成包括基于氧化硅的材料的第三绝缘膜图案，并且在布线上形成用于限定接触孔区域的侧壁上的接触图形和间隔物。 接触孔接触第三绝缘膜图案的表面并穿过第一绝缘膜。 因此，可以使布线中使用的第二绝缘膜图案的厚度最小化，从而增加布线之间的间隙填充余量。 由于在布线的侧壁上形成具有低介电常数的氧化硅间隔物，所以布线之间的寄生电容可以减小。

公开(公告)号：US20050226924A1

公开(公告)日：2005-10-13

申请号：US10902713

申请日：2004-07-29

申请人： Kyu-Hyun Lee ,  Eun-Seok Park ,  Sang-Cheol Chi

发明人： Kyu-Hyun Lee ,  Eun-Seok Park ,  Sang-Cheol Chi

IPC分类号： A61K9/14 ,  A61K9/16 ,  A61K9/20 ,  A61K31/496 ,  A61K31/497 ,  A61K47/12 ,  A61K47/38

CPC分类号： A61K9/2013 ,  A61K9/1617 ,  A61K9/1652 ,  A61K9/1676 ,  A61K9/2054 ,  A61K31/496

摘要： The present invention relates to a composition comprising itraconazole for oral administration, more precisely, a composition for oral administration containing 1 part by weight itraconazole, 0.1-0.5 part by weight citric acid and 0.1-0.5 part by weight hydroxypropylmethylcellulose. The composition of the present invention has the advantages of mitigating discomfort of administration by reducing the amount of the additives used to make itraconazole water-soluble, lowering the production price by shortening processing time of spray-drying, high solubility and dissolution rate, excellent reproducibility and stability.

摘要翻译： 本发明涉及含有伊曲康唑用于口服给药的组合物，更准确地说，涉及含有伊曲康唑1重量份，0.1-0.5重量份柠檬酸和0.1-0.5重量份羟丙基甲基纤维素的口服组合物。 本发明的组合物具有通过减少用于制造伊曲康唑水溶性的添加剂的用量来减轻给药的不适的优点，通过缩短喷雾干燥的处理时间，高溶解度和溶解速度，优异的再现性降低了生产价格 和稳定性。

公开(公告)号：US06607983B1

公开(公告)日：2003-08-19

申请号：US09707353

申请日：2000-11-06

申请人： Kwang-Youl Chun ,  Yun-Jae Lee ,  Won-Seong Lee ,  Jeong-Hoon Oh ,  Kyu-Hyun Lee

发明人： Kwang-Youl Chun ,  Yun-Jae Lee ,  Won-Seong Lee ,  Jeong-Hoon Oh ,  Kyu-Hyun Lee

IPC分类号： H01L21461

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76838 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

摘要： The present invention provides a method of eliminating or covering a defect source in a wafer edge region for semiconductor fabrication. During the etching process of a sacrificial oxide layer for storage node openings, the sacrificial oxide layer has a rumple topology in the wafer edge region due to etching non-uniformity of a photoresist layer formed on the sacrificial oxide layer. Subsequent deposition of a conductive layer and planarization etching, the conductive layer undesirably remains at the wafer edge region as a defect source. Such conductive contaminant particles dislodge, causing many problems in the wafer main region. The present invention removes such a defect source via two methods. One is to directly remove the defect source using a photoresist pattern exposing thereof. The other is to fix the defect source in place in the wafer edge region by protecting thereof by a photoresist pattern during subsequent cleaning processes.

摘要翻译： 本发明提供一种消除或覆盖用于半导体制造的晶片边缘区域中的缺陷源的方法。 在用于存储节点开口的牺牲氧化物层的蚀刻工艺期间，由于蚀刻在牺牲氧化物层上形成的光致抗蚀剂层的不均匀性，牺牲氧化物层在晶片边缘区域中具有隆起的拓扑结构。 随后沉积导电层和平坦化蚀刻，导电层不期望地保留在晶片边缘区域作为缺陷源。 这种导电性污染物颗粒移动，在晶片主区域引起许多问题。 本发明通过两种方法去除这种缺陷源。 一个是使用其曝光的光致抗蚀剂图案直接去除缺陷源。 另一种是通过在随后的清洁过程中通过光致抗蚀剂图案的保护来将缺陷源固定在晶片边缘区域中。

公开(公告)号：US08729675B1

公开(公告)日：2014-05-20

申请号：US13763927

申请日：2013-02-11

申请人： Jay-Bok Choi ,  Kyu-Hyun Lee ,  Mi-Jeong Jang ,  Young-Jin Choi ,  Ju-Young Huh

发明人： Jay-Bok Choi ,  Kyu-Hyun Lee ,  Mi-Jeong Jang ,  Young-Jin Choi ,  Ju-Young Huh

IPC分类号： H01L29/40

CPC分类号： H01L23/49838 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10847 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.

摘要翻译： 半导体器件包括彼此平行的多个平行沟槽，彼此平行的多个相交沟槽，由平行沟槽和交叉沟槽约束的多个有源区域，一个 穿过有源区的多个下导电线，彼此平行的多个上导线，穿过下导电线，并跨越有源区，以及连接到有源区的数据存储元件。 每个平行沟槽和交叉沟槽都是直线。 平行沟槽穿过上导电线并与上导线形成第一锐角。 交叉沟槽与平行沟槽交叉并与平行沟槽形成第二锐角。

公开(公告)号：US06602773B2

公开(公告)日：2003-08-05

申请号：US09840741

申请日：2001-04-23

申请人： Kyu-Hyun Lee ,  Yoon-Soon Chun

发明人： Kyu-Hyun Lee ,  Yoon-Soon Chun

IPC分类号： H01L213205

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of methods of fabricating protected contact plugs include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming an electrically conductive lower barrier layer that lines at least an upper portion of a sidewall of the contact hole. This lower barrier layer may comprise titanium nitride (TiN). A step is also performed to form an electrically conductive contact plug that extends in the contact hole, is electrically coupled to the lower barrier layer and protrudes above the electrically insulating layer. The contact plug may comprise tungsten (W). An electrically conductive upper barrier layer is then formed that extends on a protruded upper surface of the contact plug and on a surface of the lower barrier layer. A step may then be performed to pattern the upper barrier layer to define an electrically conductive barrier spacer that extends on a sidewall or end of the lower barrier layer and define an upper barrier layer cap on the protruded upper surface of the contact plug.

摘要翻译： 制造受保护的接触插塞的方法的实施例包括在半导体衬底上形成其中具有接触孔的电绝缘层，然后形成在接触孔的侧壁的至少上部分上的导电下阻挡层。 该下阻挡层可以包括氮化钛（TiN）。 还执行步骤以形成在接触孔中延伸的导电接触插塞，电连接到下阻挡层并突出在电绝缘层上方。 接触塞可以包括钨（W）。 然后形成导电上阻挡层，其在接触插塞的突出的上表面上延伸并且在下阻挡层的表面上延伸。 然后可以执行步骤以图案化上阻挡层以限定在下阻挡层的侧壁或端部上延伸并且在接触插塞的突出的上表面上限定上阻挡层帽的导电阻挡间隔物。

公开(公告)号：US06485743B1

公开(公告)日：2002-11-26

申请号：US09582536

申请日：2000-06-29

申请人： Jae-Young Jung ,  Kye-Hyun Kim ,  Sang-Heon Lee ,  Ji-Woong Hong ,  Jong-Woo Park ,  Kyu-Hyun Lee

发明人： Jae-Young Jung ,  Kye-Hyun Kim ,  Sang-Heon Lee ,  Ji-Woong Hong ,  Jong-Woo Park ,  Kyu-Hyun Lee

IPC分类号： A61K920

CPC分类号： A61K31/496 ,  A61K9/146 ,  A61K9/1635 ,  A61K9/1652

摘要： The present invention relates to a method and composition of an oral preparation of itraconazole, an excellent azole antifungal drug. More particularly, it relates to an oral preparation of itraconazole having improved bioavailability, which is prepared by following steps of: i) dissolving itraconazole and bydrophilic polymer with solvent, ii) spray-drying said mixture, and iii) preparing the solid dispersions for oral preparation. The solid dispersions prepared in this invention may be useful in preparing tablets, granules and other oral dosage forms.

摘要翻译： 本发明涉及伊曲康唑口服制剂的方法和组合物，优良的唑类抗真菌药物。 更具体地说，本发明涉及伊曲康唑具有改善的生物利用度的口服制剂，其通过以下步骤制备：i）用溶剂溶解伊曲康唑和嗜中性聚合物，ii）喷雾干燥所述混合物，和iii）制备用于口服的固体分散体 制备。 本发明制备的固体分散体可用于制备片剂，颗粒剂和其它口服剂型。

公开(公告)号：US06607955B2

公开(公告)日：2003-08-19

申请号：US09825346

申请日：2001-04-04

申请人： Kyu-Hyun Lee

发明人： Kyu-Hyun Lee

IPC分类号： H01L218242

CPC分类号： H01L21/76897 ,  H01L21/32139

摘要： A method of forming self-aligned contacts in a semiconductor device wherein a silicon nitride layer and a polysilicon layer are formed on a gate electrode layer. The polysilicon layer, the silicon nitride layer, and the gate electrode layer are etched to form gate electrode configurations. Sidewall spacers are formed on both sidewalls of the gate electrode configurations. An oxide layer is then deposited on the resulting structure. Selected portions of the oxide layer are etched to form self-aligned contacts that expose the semiconductor substrate. Because the polysilicon has an excellent etch selectivity with respect to the oxide layer, the gate electrode layer can be sufficiently protected during the etching of the oxide layer resulting in a good shoulder margin at the exposed upper edges of the silicon nitride gate mask layer.

摘要翻译： 在半导体器件中形成自对准接触的方法，其中在栅电极层上形成氮化硅层和多晶硅层。 蚀刻多晶硅层，氮化硅层和栅电极层以形成栅电极构造。 侧壁间隔物形成在栅电极构造的两个侧壁上。 然后在所得结构上沉积氧化物层。 蚀刻氧化物层的选定部分以形成露出半导体衬底的自对准接触。 由于多晶硅相对于氧化物层具有优异的蚀刻选择性，所以在蚀刻氧化物层期间可以充分保护栅电极层，从而在氮化硅栅极掩模层的暴露的上边缘处产生良好的肩部边缘。

公开(公告)号：US06337275B1

公开(公告)日：2002-01-08

申请号：US09334669

申请日：1999-06-17

申请人： Chang-Hyun Cho ,  Kyu-Hyun Lee ,  Jae-Goo Lee ,  Sang-Sup Jeong

发明人： Chang-Hyun Cho ,  Kyu-Hyun Lee ,  Jae-Goo Lee ,  Sang-Sup Jeong

IPC分类号： H01L2144

CPC分类号： H01L21/76897 ,  H01L21/76834

摘要： A self aligned contact (SAC) pad in a semiconductor device and a method for forming thereof wherein an SAC opening is formed concurrently with single-layer gate spacers. After formation of the stacked gate pattern having a gate electrode and a capping layer disposed thereon, an insulating layer for gate spacers is deposited thereon. An interlayer insulating layer then is deposited over the insulating layer. The interlayer insulating layer has an etch selectivity with respect to the capping layer and insulating layer. SAC then are opened in the interlayer insulating layer while concurrently forming single-layer gate spacers.

摘要翻译： 半导体器件中的自对准接触（SAC）焊盘及其形成方法，其中SAC开口与单层栅极间隔物同时形成。 在形成具有设置在其上的栅电极和覆盖层的堆叠栅极图案之后，在其上沉积栅极间隔物的绝缘层。 然后在绝缘层上沉积层间绝缘层。 层间绝缘层相对于覆盖层和绝缘层具有蚀刻选择性。 然后在层间绝缘层中打开SAC，同时形成单层栅极间隔物。