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    Organic electroluminescence display device and method of fabricating the same
    2.
    发明授权
    Organic electroluminescence display device and method of fabricating the same 有权
    有机电致发光显示装置及其制造方法

    公开(公告)号：US07671530B2

    公开(公告)日：2010-03-02

    申请号：US11641002

    申请日：2006-12-19

    申请人： Jae Yong Park ,  Kwang Jo Hwang ,  Jong Woo Park ,  Hee Dong Choi ,  Sang Ho Yu ,  Jin Hyoung Kim

    发明人： Jae Yong Park ,  Kwang Jo Hwang ,  Jong Woo Park ,  Hee Dong Choi ,  Sang Ho Yu ,  Jin Hyoung Kim

    IPC分类号： H01J1/62

    CPC分类号： H01L27/3276 ,  H01L27/3251

    摘要： Provided are an organic electroluminescence display device and method of fabricating the same. An organic electroluminescence display device according to the present invention includes a first substrate; a plurality of data lines arranged in a first direction on the first substrate; a plurality of gate lines arranged in a second direction on the first substrate; a plurality of pixel regions defined by the gate lines and the data lines, wherein a first pixel line is defined as a line of the pixel regions arranged in the first direction and a second pixel line is defined as a line of the pixel regions arranged in the second direction; a thin film transistor in each pixel region; a plurality of first connecting lines electrically connecting the thin film transistors of the first pixel lines with each other; and a second connecting line electrically connecting the thin film transistor of at least one of the second pixel lines.

    摘要翻译： 提供一种有机电致发光显示装置及其制造方法。 根据本发明的有机电致发光显示装置包括第一基板; 在第一基板上沿第一方向布置的多条数据线; 在所述第一基板上沿第二方向布置的多个栅极线; 由栅极线和数据线限定的多个像素区域，其中第一像素线被定义为沿第一方向布置的像素区域的线，而第二像素线被定义为布置在其中的像素区域的线 第二个方向 每个像素区域中的薄膜晶体管; 将第一像素线的薄膜晶体管彼此电连接的多个第一连接线; 以及第二连接线，电连接至少一个第二像素线的薄膜晶体管。

    Liquid crystal display device and fabricating method having reflective electrode connecting pixel electrode with drain and upper storage capacitor electrodes at edge of transmission hole
    3.
    发明授权
    Liquid crystal display device and fabricating method having reflective electrode connecting pixel electrode with drain and upper storage capacitor electrodes at edge of transmission hole 有权
    具有反射电极的液晶显示装置及其制造方法，该反射电极将透明孔的边缘处的漏极和上部存储电容器电极的像素电极连接

    公开(公告)号：US07528909B2

    公开(公告)日：2009-05-05

    申请号：US11139501

    申请日：2005-05-31

    申请人： Byung Chul Ahn ,  Jong Woo Park

    发明人： Byung Chul Ahn ,  Jong Woo Park

    IPC分类号： G02F1/1335

    CPC分类号： G02F1/13458 ,  G02F1/133555 ,  G02F1/13624 ,  G02F2001/136231 ,  G02F2001/136236 ,  G02F2001/13629

    摘要： A method of fabricating a LCD device includes forming a gate line, a gate electrode, and a pixel electrode having a double-layer structure on a first substrate using a first mask, the double-layer structure including first and second conductive layers; forming a first insulation film, a semiconductor pattern on the first insulation film, a source/drain pattern having an upper storage electrode, source and drain electrodes, a data line using a second mask, the data and gate lines defining a pixel region having transmission and reflection areas; forming a second insulation film on the source/drain pattern and a transmission hole by passing through the second insulation film to the second conductive layer in the transmission area using a third mask; and forming a reflective electrode in the reflection area using a fourth mask, the reflective electrode connecting the pixel electrode with the drain electrode and the storage electrode.

    摘要翻译： 一种制造LCD器件的方法包括：使用第一掩模在第一衬底上形成具有双层结构的栅极线，栅电极和像素电极，所述双层结构包括第一和第二导电层; 形成第一绝缘膜，第一绝缘膜上的半导体图案，具有上部存储电极的源极/漏极图案，源极和漏极，使用第二掩模的数据线，限定具有透射的像素区域的数据线和栅极线 和反射区域; 在所述源极/漏极图案上形成第二绝缘膜，通过使用第三掩模将所述第二绝缘膜穿过所述透射区域中的所述第二导电层，形成透射孔; 以及使用第四掩模在所述反射区域中形成反射电极，所述反射电极将所述像素电极与所述漏电极和所述存储电极连接。

    Non-volatile memory device with protruding charge storage layer and method of fabricating the same
    5.
    发明授权
    Non-volatile memory device with protruding charge storage layer and method of fabricating the same 失效
    具有突出电荷存储层的非易失性存储器件及其制造方法

    公开(公告)号：US07081651B2

    公开(公告)日：2006-07-25

    申请号：US10186153

    申请日：2002-06-27

    申请人： Jung-Dal Choi ,  Jong-Woo Park ,  Seong-Soon Cho ,  Chang-Hyun Lee

    发明人： Jung-Dal Choi ,  Jong-Woo Park ,  Seong-Soon Cho ,  Chang-Hyun Lee

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    摘要： A non-volatile memory device includes a tunnel oxide layer, a charge storage layer, a blocking insulating layer, and a gate electrode that are sequentially stacked, as well as an impurity diffusion layer in an active region at both sides of the gate electrode. The gate electrode crosses active regions between device isolation layers formed in a predetermined area of a semiconductor substrate, and an edge of the charge storage layer is extended to have a protruding part that protrudes from the gate electrode. In order to form a charge storage layer having a protruding part, a stack insulating layer including first to third insulating layers is formed in an active region between the device isolation layers formed in the substrate. A plurality of gate electrodes crossing the active region are formed on the stack insulating layer, and a sidewall spacer is formed on both sidewalls of the gate electrode. Using the sidewall spacer and the gate electrode, the stack insulating layer is etched to form a charge storage layer that protrudes from the sidewall of the gate electrode.

    摘要翻译： 非易失性存储器件包括顺序层叠的隧道氧化物层，电荷存储层，阻挡绝缘层和栅电极，以及栅电极两侧的有源区中的杂质扩散层。 栅电极跨越形成在半导体衬底的预定区域中的器件隔离层之间的有源区，并且电荷存储层的边缘延伸成具有从栅电极突出的突出部分。 为了形成具有突出部分的电荷存储层，在形成在衬底中的器件隔离层之间的有源区域中形成包括第一至第三绝缘层的叠层绝缘层。 在堆叠绝缘层上形成与激活区交叉的多个栅电极，并且在栅电极的两个侧壁上形成侧墙。 使用侧壁间隔物和栅电极，对叠层绝缘层进行蚀刻以形成从栅电极的侧壁突出的电荷存储层。

    Methods of forming self-aligned contact structures in semiconductor integrated circuit devices
    6.
    发明授权
    Methods of forming self-aligned contact structures in semiconductor integrated circuit devices 有权
    在半导体集成电路器件中形成自对准接触结构的方法

    公开(公告)号：US06881659B2

    公开(公告)日：2005-04-19

    申请号：US10656935

    申请日：2003-09-05

    申请人： Jong-Woo Park ,  Yun-Gi Kim ,  Dong-Gun Park

    发明人： Jong-Woo Park ,  Yun-Gi Kim ,  Dong-Gun Park

    IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/4763

    CPC分类号： H01L27/10855 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10885

    摘要： Methods of forming integrated circuit devices (e.g., memory devices) include the use of preferred self-aligned contact hole fabrication steps. These steps improve process reliability by reducing the likelihood that contact holes will become misaligned to underlying integrated circuit device structures and thereby potentially expose the structures in an adverse manner. Typical methods include the steps of forming a plurality of interconnection patterns on a substrate and then covering a surface of the interconnection patterns and a portion of the substrate with a capping insulating layer such as silicon nitride layer. The capping insulating layer is then covered with an upper interlayer insulating layer different from the capping insulating layer. The upper interlayer insulating layer and the capping insulating layer are then dry-etched in sequence to form a first narrow contact hole that exposes the substrate, but preferably does not expose the interconnection patterns. The first contact hole is then widened in a self-aligned manner using the capping insulating layer as an etch-stop layer. This widening step is performed by wet etching sidewalls of the first contact hole using an etchant that etches the upper interlayer insulating layer faster than the capping insulating layer. In this manner, the first contact hole may be formed to initially compensate for potential misalignment errors and then a self-aligned wet etching step may be performed to widen the first contact hole into a second contact hole so that low resistance contacts (e.g., contact plugs) can be provided therein.

    摘要翻译： 形成集成电路器件（例如，存储器件）的方法包括使用优选的自对准接触孔制造步骤。 这些步骤通过减少接触孔将变得不对准到下面的集成电路器件结构并由此以不利的方式潜在地暴露结构的可能性来提高工艺可靠性。 典型的方法包括以下步骤：在衬底上形成多个互连图案，然后用诸如氮化硅层的覆盖绝缘层覆盖互连图案的表面和衬底的一部分。 然后用与封盖绝缘层不同的上层间绝缘层覆盖封盖绝缘层。 然后依次对上层间绝缘层和封盖绝缘层进行干式蚀刻，形成露出基板的第一窄接触孔，但优选不暴露互连图案。 然后使用封盖绝缘层作为蚀刻停止层，以自对准的方式加宽第一接触孔。 通过使用蚀刻上层间绝缘层的蚀刻剂比封盖绝缘层更快地湿蚀刻第一接触孔的侧壁来进行该扩大步骤。 以这种方式，可以形成第一接触孔以最初补偿潜在的未对准误差，然后可以执行自对准的湿蚀刻步骤，以将第一接触孔加宽成第二接触孔，使得低电阻接触（例如，接触 插头）。

    Flash memory device with isolation regions and a charge storage dielectric layer formed only on an active region
    7.
    发明授权
    Flash memory device with isolation regions and a charge storage dielectric layer formed only on an active region 有权
    具有隔离区域的闪存器件和仅在有源区域上形成的电荷存储电介质层

    公开(公告)号：US06784481B2

    公开(公告)日：2004-08-31

    申请号：US10098875

    申请日：2002-03-15

    申请人： You-Cheol Shin ,  Jong-Woo Park ,  Jung-Dal Choi

    发明人： You-Cheol Shin ,  Jong-Woo Park ,  Jung-Dal Choi

    IPC分类号： H01L2976

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

    摘要： A flash memory having a charge-storage dielectric layer. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.

    摘要翻译： 具有电荷存储介电层的闪速存储器。 根据一个实施例，电荷存储电介质层形成在第一和第二有源区上。 第一有源区上的电荷存储层在第二有源区上并未连接到电荷存储层。 栅极线覆盖电荷存储层并且延伸穿过第一和第二有源区域和隔离区域。 电荷存储层只能在栅极线与半导体衬底的有源区相交而不在隔离区上形成。 因此，可以避免来自相邻存储单元的不期望​​的影响或干扰。

    Continuous shear deformation device
    8.
    发明授权
    Continuous shear deformation device 失效
    连续剪切变形装置

    公开(公告)号：US06370930B1

    公开(公告)日：2002-04-16

    申请号：US09638761

    申请日：2000-08-15

    申请人： Jae-Chul Lee ,  Hyun-Kwang Seok ,  Jong-Woo Park ,  Young-Hoon Chung ,  Ho-In Lee

    发明人： Jae-Chul Lee ,  Hyun-Kwang Seok ,  Jong-Woo Park ,  Young-Hoon Chung ,  Ho-In Lee

    IPC分类号： B21C2300

    CPC分类号： B21C23/005 ,  B21C23/001

    摘要： The present invention relates to a continuous shear deformation device. In order to occur shear deformation at the position at which a material is inserted into a molding path from a rotary guide apparatus for the purpose of solving the problem that the amount of shear deformation of a material is non-uniform and insufficient due to the gap between the curved portion of the molding path and the lower parts of the material, there is provided a continuous shear deformation device, characterized in that a curved portion is constructed by collaboration between the rotary guide apparatus and the molding path. In addition, there are provided additional constructions for effectively performing shear deformation by a small power by reducing the friction at the molding path excepting the curved portion. The present invention thusly constructed can be utilized for continuously and effectively mass-produce sheared materials.

    摘要翻译： 本发明涉及连续剪切变形装置。 为了解决材料的剪切变形量由于间隙而不均匀和不足的问题，为了在从旋转引导装置插入到模制路径中的位置处发生剪切变形 在模制路径的弯曲部分和材料的下部之间提供连续的剪切变形装置，其特征在于，通过旋转导向装置和模制路径之间的协作构造弯曲部分。 此外，还提供了通过减小​​除了弯曲部分之外的模制路径处的摩擦力来通过小功率有效地执行剪切变形的附加结构。 这样构造的本发明可以用于连续且有效地大量生产剪切材料。

    Dieless forming apparatus
    9.
    发明授权
    Dieless forming apparatus 失效
    无形成型装置

    公开(公告)号：US6151938A

    公开(公告)日：2000-11-28

    申请号：US454769

    申请日：1999-12-03

    申请人： Jong-Woo Park ,  Yeh-Sun Hong ,  Soon-Ho Lim

    发明人： Jong-Woo Park ,  Yeh-Sun Hong ,  Soon-Ho Lim

    IPC分类号： B21D13/00 ,  B21D22/10 ,  B21D37/02 ,  B21D11/20

    CPC分类号： B21D22/10 ,  B21D37/02

    摘要： The present invention relates to an advanced forming apparatus for sheet blanks such as sheet metals or plastics, and in particular to a multi-purpose and multi-functional forming apparatus which can form sheets into products of various curved surface shape without using a die. The dieless forming apparatus includes an elastomer installed on one side of the sheet blank; a group of punches disposed at the opposite side of the blank, and having ends of various shapes applying a force to the formed material by movement; and a control unit controlling the movement of the press. In addition, a fluid may be filled in substitute for a part of the elastomer to evenly apply a force to the formed material, and a fluid control unit may be included to control a fluid pressure.

    摘要翻译： 本发明涉及一种用于诸如金属板或塑料的板坯的先进成型装置，特别涉及一种多功能和多功能成型装置，它可以在不使用模具的情况下将片材形成为各种曲面形状的产品。 该无缝成形装置包括安装在板坯的一侧的弹性体; 设置在坯料的相对侧的一组冲头，并且具有通过运动向成形材料施加力的各种形状的端部; 以及控制压力机的运动的控制单元。 此外，可以填充流体来代替一部分弹性体以均匀地向成形材料施加力，并且可以包括流体控制单元以控制流体压力。

    Method of manufacturing buried bit line DRAM cell
    10.
    发明授权
    Method of manufacturing buried bit line DRAM cell 失效
    掩埋位线DRAM单元的制造方法

    公开(公告)号：US5840591A

    公开(公告)日：1998-11-24

    申请号：US565029

    申请日：1995-11-30

    申请人： Jae-Kwan Park ,  Jong-Woo Park

    发明人： Jae-Kwan Park ,  Jong-Woo Park

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10844 ,  H01L27/10805 ,  H01L27/10808

    摘要： A buried bit line DRAM cell and a manufacturing method thereof are provided. The buried bit line DRAM cell has a buried bit line formed into a trench which isolates devices, the buried bit line being isolated from a semiconductor substrate, a gate formed to be orthogonal to the bit line on the substrate, a first insulating layer formed to insulate the gate, a source and a drain of a transistor formed on the substrate at both sides of the gate, a self-aligned bit line contact formed between the first insulating layers for making contact between the drain and the buried bit line, and a self-aligned buried contact formed between the first insulating layers for making contact between the source and a storage electrode. According to the above structure, misalignment between the gate and the bit line and the excessive exposure to thermal processing which are inherent in conventional Buried Bit Line cells can be avoided and the design rule margin can be improved.

    摘要翻译： 提供了掩埋位线DRAM单元及其制造方法。 掩埋位线DRAM单元具有形成沟槽的掩埋位线，隔离器件，掩埋位线与半导体衬底隔离，形成为与衬底上的位线正交的栅极;第一绝缘层，形成为 在门的两侧将形成在衬底上的晶体管的源极和漏极绝缘，形成在第一绝缘层之间以在漏极和掩埋位线之间接触的自对准位线接触，以及 在第一绝缘层之间形成的用于使源极与存储电极接触的自对准埋入触点。 根据上述结构，可以避免常规掩埋位线单元中固有的栅极和位线之间的偏移和过热暴露于热处理，并且可以提高设计规则裕度。