公开(公告)号：US09356137B2

公开(公告)日：2016-05-31

申请号：US14130483

申请日：2013-05-07

Applicant: CSMC Technologies Fab1 Co., Ltd.

Inventor： Shu Zhang ,  Yanqiang He ,  TseHuang Lo ,  HsiaoChia Wu

IPC: H01L29/78 ,  H01L23/00 ,  H01L23/482

CPC classification number: H01L29/7816 ,  H01L23/4824 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/07 ,  H01L24/08 ,  H01L24/09 ,  H01L29/7835 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.

Abstract translation: 公开了功率MOS器件结构的各种实施例。 一方面，功率MOS器件结构包括多个LDMOS和多个接合焊盘。 LDMOS的基本单元并联并电耦合到焊盘，以耦合到LDMOS的每个基本单元的栅极端子，源极端子，漏极端子和衬底。 LDMOS的基本单元设置在焊盘下方。 接合焊盘包括厚度为3.5μm至4.5μm，宽度为1.5μm至2.5μm的单层金属。 本公开的功率MOS器件的焊盘下方的区域用于增加LDMOS的基本单元的数量，从而有效地降低导通电阻。

公开(公告)号：US09236306B2

公开(公告)日：2016-01-12

申请号：US14130476

申请日：2012-11-28

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Hsiaochia Wu ,  Shilin Fang ,  Tsehuang Lo ,  Zhengpei Chen ,  Shu Zhang ,  Yanqiang He

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823412 ,  H01L21/823456 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922

Abstract: A method for manufacturing a semiconductor device according to this specification solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The method is applicable to a BCD process and the like.

Abstract translation: 根据本说明书的制造半导体器件的方法解决了现有技术中的问题，即LDMOS漂移区域中的氧化物层的边缘上的硅容易暴露并导致LDMOS器件的击穿。 该方法包括：提供包括LDMOS区域和CMOS区域的半导体衬底; 在所述半导体衬底上形成牺牲氧化物层; 去除牺牲氧化物层; 在牺牲氧化处理后在半导体衬底上形成掩模层; 使用掩模层作为掩模形成LDMOS漂移区，以及在漂移区上方形成漂移区氧化物层; 并去除掩模层。 该方法适用于BCD处理等。

公开(公告)号：US20140147980A1

公开(公告)日：2014-05-29

申请号：US14130476

申请日：2012-11-28

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Hsiaochia Wu ,  Shilin Fang ,  Tsehuang Lo ,  Zhengpei Chen ,  Shu Zhang ,  Yanqiang He

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823412 ,  H01L21/823456 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922

Abstract: The present invention relates to the technical field of semiconductor manufacturing. A method for manufacturing a semiconductor device is disclosed, which solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The embodiment of the present invention is applicable to a BCD process and the like.

Abstract translation: 本发明涉及半导体制造技术领域。 公开了一种用于制造半导体器件的方法，其解决了现有技术中在LDMOS漂移区域中的氧化物层的边缘上的硅容易暴露并导致LDMOS器件破坏的问题。 该方法包括：提供包括LDMOS区域和CMOS区域的半导体衬底; 在所述半导体衬底上形成牺牲氧化物层; 去除牺牲氧化物层; 在牺牲氧化处理后在半导体衬底上形成掩模层; 使用掩模层作为掩模形成LDMOS漂移区，以及在漂移区上方形成漂移区氧化物层; 并去除掩模层。 本发明的实施例可应用于BCD处理等。