公开(公告)号：US20210167190A1

公开(公告)日：2021-06-03

申请号：US16771168

申请日：2018-11-13

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Guipeng SUN

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.

公开(公告)号：US20240304720A1

公开(公告)日：2024-09-12

申请号：US18576942

申请日：2022-12-14

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Liang SONG ,  Yongshun LI ,  Mei YUAN ,  Yanan WANG ,  Lin LUO ,  Qiang ZHANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0603 ,  H01L29/66681

Abstract: The present disclosure involves a semiconductor device and a manufacturing method thereof. A second well region is inserted between first well regions of a semiconductor device to improve the breakdown voltage of the device, and at the same time, the dimension of the upper surface of the second well region in the width direction of the device's conductive channel is set to be smaller than the dimension of the lower surface of the second well region in the width direction of the device's conductive channel to increase the dimension of the upper surface of the adjacent first well region in the width direction of the device's conductive channel. That is, the path width of the current flowing through the upper surface of the drift region is increased when the device is on, and thus the device's on-resistance is reduced.

公开(公告)号：US20240006477A1

公开(公告)日：2024-01-04

申请号：US18254986

申请日：2022-07-22

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yongshun LI ,  Huajun JIN ,  Liang SONG

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36

CPC classification number: H01L29/0634 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/36

Abstract: A manufacturing method for a super-β bipolar junction transistor includes providing a substrate, and forming a first conductive type isolation buried layer and a first conductive type doped layer based on the substrate. The isolation buried layer is located at a bottom of the doped layer. The method also includes forming a second conductive type base region in the doped layer and forming a second conductive type doped island on a peripheral side of the base region. A doping concentration of the doped island is greater than that of the base region. Additionally, the method includes forming a first conductive type collector region in the doped layer, and the collector region is spaced from the base region. Further, the method includes forming a first conductive type emitter region in the base region.

公开(公告)号：US20230163177A1

公开(公告)日：2023-05-25

申请号：US17766406

申请日：2020-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Guipeng SUN

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/404 ,  H01L29/401 ,  H01L29/7816 ,  H01L29/66681

Abstract: The present invention relates to an LDMOS device and a method of forming the device, in which a barrier layer includes n etch stop layers. Insulating layers are formed between adjacent etch stop layers. Since an interlayer dielectric layer and the insulating layers are both oxides that differ from the material of the etch stop layers, etching processes can be stopped at the n etch stop layers when they are proceeding in the oxides, thus forming n field plate holes terminating at the respective n etch stop layers. A lower end of the first field plate hole proximal to a gate structure is closest to a drift region, and a lower end of the n-th field plate hole proximal to a drain region is farthest from the drift region. With this arrangement, more uniform electric field strength can be obtained around front and rear ends of the drift region, resulting in an effectively improved electric field distribution throughout the drift region and thus in an increased breakdown voltage.

公开(公告)号：US20190378912A1

公开(公告)日：2019-12-12

申请号：US16462432

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Guipeng SUN

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device, includes: forming a well region (201) in a semiconductor substrate (200) and forming a channel region (202) in the well region (201), and forming a gate oxide layer (210) and a polysilicon layer (220) on the well region (201); etching a portion of the gate oxide layer (210) and the polysilicon layer (220), and exposing a first opening (221) used for forming a source region and a second opening (223) used for forming a drain region; forming a first dielectric layer (230) and a second dielectric layer (240) on the polysilicon layer (220) and in the first opening (221) and the second opening (223) successively, and forming a source region side wall at a side surface of the first opening (221) and forming a drain region side wall at a side surface of the second opening (223); forming a dielectric oxide layer (250) on the polysilicon layer (220), etching the dielectric oxide layer and retaining the dielectric oxide layer (250) located on the drain region side wall; removing the second dielectric layer (240) in the source region side wall and retaining the first dielectric layer (230) therein.

公开(公告)号：US20220384641A1

公开(公告)日：2022-12-01

申请号：US17886609

申请日：2022-08-12

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Guipeng SUN ,  Feng LIN ,  Shuxian CHEN

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/266

Abstract: A method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a semiconductor substrate of a first conductivity type, forming a deep well of a second conductivity type in the semiconductor substrate, forming a channel region of the first conductivity type, a first well region of the first conductivity type, and a drift region of the second conductivity type in the deep well, the first well region and the channel region being spaced by a portion of the deep well, the drift region being located between the channel region and the first well region, forming an ion implantation region of the first conductivity type in the deep well, the ion implantation region being located under the drift region, and forming a source region of the second conductivity type and a drain region of the second conductivity type in the deep well.

公开(公告)号：US20220262948A1

公开(公告)日：2022-08-18

申请号：US17631287

申请日：2020-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Chunxu LI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40

Abstract: The present invention relates to an LDMOS device and a method for preparing same. When a field plate hole is formed by etching an interlayer dielectric layer, the etching of the field plate hole is stopped on a blocking layer by means of providing the blocking layer between a semiconductor base and the interlayer dielectric layer. Since the blocking layer is provided with at least one layer of an etch stop layer, and steps are formed on the surface of the blocking layer, at least two levels of formed hole field plates are distributed in a step shape, and lower ends of the first level of hole field plates to the nth level of hole field plates are gradually further away from the drift area in the direction from a gate structure to a drain area.

公开(公告)号：US20200220010A1

公开(公告)日：2020-07-09

申请号：US16644856

申请日：2018-08-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Guipeng SUN ,  Hongfeng JIN

IPC: H01L29/78 ,  H01L29/66

Abstract: Provided in the present invention are an LDMOS component, a manufacturing method therefor, and an electronic device, comprising: a semiconductor substrate (100); a drift area (101) provided in the semiconductor substrate; a gate electrode structure (103) provided on a part of the surface of the semiconductor substrate and covers a part of the surface of the drift area; a source electrode (1052) and a drain electrode (1051) respectively provided in the semiconductor substrate on either side of the gate electrode structure, where the drain electrode is provided in the drift area and is separated from the gate electrode structure; a metal silicide barrier layer (106) covering the surface of at least a part of the semiconductor substrate between the gate electrode structure and the drain electrode; and a first contact hole (1081) provided on the surface of at least a part of the metal silicide barrier layer.