公开(公告)号：US08502341B2

公开(公告)日：2013-08-06

申请号：US13021333

申请日：2011-02-04

申请人： Chul Lee ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

发明人： Chul Lee ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

IPC分类号： H01L29/92

CPC分类号： H01L29/92

摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.

摘要翻译： 提供了沟槽型电容器。 为了形成电容器，第一和第二有源区域设置在半导体衬底中。 节点图案设置在第一活动区域中。 每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。 杂质扩散区域设置在节点图案附近。 设置与第一和第二有源区电接触的衬底连接图案。 与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。 此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

公开(公告)号：US20110210421A1

公开(公告)日：2011-09-01

申请号：US13021333

申请日：2011-02-04

申请人： CHUL LEE ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

发明人： CHUL LEE ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

IPC分类号： H01L29/92

CPC分类号： H01L29/92

摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.

摘要翻译： 提供了沟槽型电容器。 为了形成电容器，第一和第二有源区域设置在半导体衬底中。 节点图案设置在第一活动区域中。 每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。 杂质扩散区域设置在节点图案附近。 设置与第一和第二有源区电接触的衬底连接图案。 与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。 此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

公开(公告)号：US20120139021A1

公开(公告)日：2012-06-07

申请号：US13241435

申请日：2011-09-23

申请人： Seok-Hyun Kim ,  Deok-Sung Hwang ,  Yun-Jae Lee ,  Chul Lee ,  Yoon-Taek Jang ,  Chang-Hoon Jeon ,  Sang-Bin Ahn ,  Jun-Hyeok Ahn

发明人： Seok-Hyun Kim ,  Deok-Sung Hwang ,  Yun-Jae Lee ,  Chul Lee ,  Yoon-Taek Jang ,  Chang-Hoon Jeon ,  Sang-Bin Ahn ,  Jun-Hyeok Ahn

IPC分类号： H01L27/108

CPC分类号： H01L27/10876 ,  H01L21/765

摘要： A semiconductor memory device includes a transistor having a channel region buried in a substrate and source/drain regions formed to provide low contact resistance. A field isolation structure is formed in the substrate to define active structures. The field isolation structure includes a gap-fill pattern, a first material layer surrounding the gap-fill pattern, and a second material layer surrounding at least a portion of the first material layer. Each active structure includes a first active pattern having a top surface located beneath the level of the top surface of the field isolation structure, and a second active pattern disposed on the first active pattern and whose top is located above the level of the top surface of the field isolation structure.

摘要翻译： 半导体存储器件包括具有掩埋在衬底中的沟道区和形成为提供低接触电阻的源极/漏极区的晶体管。 在衬底中形成场隔离结构以限定有源结构。 场隔离结构包括间隙填充图案，围绕间隙填充图案的第一材料层和围绕第一材料层的至少一部分的第二材料层。 每个有源结构包括第一有源图案，其具有位于场隔离结构的顶表面的平面下方的顶表面，以及布置在第一有源图案上的第二有源图案，其顶部位于第一有源图案的顶表面的高度之上 现场隔离结构。

公开(公告)号：US20120214297A1

公开(公告)日：2012-08-23

申请号：US13351439

申请日：2012-01-17

申请人： Kwan-Sik Cho ,  Deok-Sung Hwang ,  Kye-Hee Yeom

发明人： Kwan-Sik Cho ,  Deok-Sung Hwang ,  Kye-Hee Yeom

IPC分类号： H01L21/28

CPC分类号： H01L29/4236 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

摘要： A method of fabricating a semiconductor device includes partially removing an active region and an isolation region to form a gate buried trench, forming a gate insulating layer on an inner wall of the gate buried trench, forming a gate conductive pattern on the gate insulating layer to fill the gate buried trench, and a height of an uppermost surface of the gate conductive pattern is lower than a height of an uppermost surface of the substrate. The method also includes forming an interlayer insulating layer on the substrate and on the gate conductive pattern, the interlayer insulating layer includes an upper insulating region and a lower insulating region, the lower insulating region fills the gate buried trench, the upper insulating region is formed over the substrate, and forming a bit contact plug connected to the active region through the interlayer.

摘要翻译： 一种制造半导体器件的方法包括部分去除有源区和隔离区以形成栅极掩埋沟槽，在栅极掩埋沟槽的内壁上形成栅极绝缘层，在栅极绝缘层上形成栅极导电图案至 填充栅极埋入沟槽，并且栅极导电图案的最上表面的高度低于衬底的最上表面的高度。 该方法还包括在基板上和栅极导电图案上形成层间绝缘层，层间绝缘层包括上绝缘区和下绝缘区，下绝缘区填充栅埋层沟槽，形成上绝缘区 并且形成通过中间层连接到活性区域的位接触塞。