公开(公告)号：US20110210421A1

公开(公告)日：2011-09-01

申请号：US13021333

申请日：2011-02-04

申请人： CHUL LEE ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

发明人： CHUL LEE ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

IPC分类号： H01L29/92

CPC分类号： H01L29/92

摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.

摘要翻译： 提供了沟槽型电容器。 为了形成电容器，第一和第二有源区域设置在半导体衬底中。 节点图案设置在第一活动区域中。 每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。 杂质扩散区域设置在节点图案附近。 设置与第一和第二有源区电接触的衬底连接图案。 与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。 此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

公开(公告)号：US08502341B2

公开(公告)日：2013-08-06

申请号：US13021333

申请日：2011-02-04

申请人： Chul Lee ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

发明人： Chul Lee ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

IPC分类号： H01L29/92

CPC分类号： H01L29/92

摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.

摘要翻译： 提供了沟槽型电容器。 为了形成电容器，第一和第二有源区域设置在半导体衬底中。 节点图案设置在第一活动区域中。 每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。 杂质扩散区域设置在节点图案附近。 设置与第一和第二有源区电接触的衬底连接图案。 与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。 此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

公开(公告)号：US20100283094A1

公开(公告)日：2010-11-11

申请号：US12840599

申请日：2010-07-21

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US08174065B2

公开(公告)日：2012-05-08

申请号：US12840599

申请日：2010-07-21

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L29/66

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US20070290258A1

公开(公告)日：2007-12-20

申请号：US11530705

申请日：2006-09-11

申请人： Youngwoong Son ,  Jae-Man Yoon ,  Bong-soo Kim ,  Hyeoungwon Seo

发明人： Youngwoong Son ,  Jae-Man Yoon ,  Bong-soo Kim ,  Hyeoungwon Seo

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/7827

摘要： Field effect transistors include a substrate and a pillar that extends away from the substrate. The pillar includes a base adjacent the substrate, a top remote from the substrate, and a sidewall that extends between the base and the top. An insulated gate is provided on the sidewall. A first source/drain region is provided in the substrate beneath the pillar and adjacent the insulated gate. A second source/drain region that is heavily doped compared to the first source/drain region, is provided in the substrate beneath the pillar and remote from the insulated gate. The pillar may be an I-shaped pillar that is narrower between the base and the top compared to adjacent the base and the top, such that the sidewall includes a recessed portion between the base and the top.

摘要翻译： 场效应晶体管包括基板和远离基板延伸的支柱。 支柱包括邻近基板的基部，远离基板的顶部以及在基部和顶部之间延伸的侧壁。 在侧壁上设置绝缘门。 第一源极/漏极区域设置在柱下方的衬底中并且邻近绝缘栅极。 与第一源极/漏极区域相比重掺杂的第二源极/漏极区域设置在支柱下方的衬底中并且远离绝缘栅极。 支柱可以是与基部和顶部相邻的基部和顶部之间较窄的I形支柱，使得侧壁包括在基部和顶部之间的凹部。

公开(公告)号：US07781285B2

公开(公告)日：2010-08-24

申请号：US11450936

申请日：2006-06-09

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US08053307B2

公开(公告)日：2011-11-08

申请号：US12662393

申请日：2010-04-14

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

公开(公告)号：US07728373B2

公开(公告)日：2010-06-01

申请号：US11705109

申请日：2007-02-12

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L21/2842

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

公开(公告)号：US07531874B2

公开(公告)日：2009-05-12

申请号：US11530705

申请日：2006-09-11

申请人： Youngwoong Son ,  Jae-Man Yoon ,  Bong-soo Kim ,  Hyeoungwon Seo

发明人： Youngwoong Son ,  Jae-Man Yoon ,  Bong-soo Kim ,  Hyeoungwon Seo

IPC分类号： H01L29/08

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/7827

摘要： Field effect transistors include a substrate and a pillar that extends away from the substrate. The pillar includes a base adjacent the substrate, a top remote from the substrate, and a sidewall that extends between the base and the top. An insulated gate is provided on the sidewall. A first source/drain region is provided in the substrate beneath the pillar and adjacent the insulated gate. A second source/drain region that is heavily doped compared to the first source/drain region, is provided in the substrate beneath the pillar and remote from the insulated gate. The pillar may be an I-shaped pillar that is narrower between the base and the top compared to adjacent the base and the top, such that the sidewall includes a recessed portion between the base and the top.

摘要翻译： 场效应晶体管包括基板和远离基板延伸的支柱。 支柱包括邻近基板的基部，远离基板的顶部以及在基部和顶部之间延伸的侧壁。 在侧壁上设置绝缘门。 第一源极/漏极区域设置在柱下方的衬底中并且邻近绝缘栅极。 与第一源极/漏极区域相比重掺杂的第二源极/漏极区域设置在支柱下方的衬底中并且远离绝缘栅极。 支柱可以是与基部和顶部相邻的基部和顶部之间较窄的I形支柱，使得侧壁包括在基部和顶部之间的凹部。

公开(公告)号：US20070284647A1

公开(公告)日：2007-12-13

申请号：US11705109

申请日：2007-02-12

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。