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    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20120139021A1

    公开(公告)日：2012-06-07

    申请号：US13241435

    申请日：2011-09-23

    申请人： Seok-Hyun Kim ,  Deok-Sung Hwang ,  Yun-Jae Lee ,  Chul Lee ,  Yoon-Taek Jang ,  Chang-Hoon Jeon ,  Sang-Bin Ahn ,  Jun-Hyeok Ahn

    发明人： Seok-Hyun Kim ,  Deok-Sung Hwang ,  Yun-Jae Lee ,  Chul Lee ,  Yoon-Taek Jang ,  Chang-Hoon Jeon ,  Sang-Bin Ahn ,  Jun-Hyeok Ahn

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10876 ,  H01L21/765

    摘要： A semiconductor memory device includes a transistor having a channel region buried in a substrate and source/drain regions formed to provide low contact resistance. A field isolation structure is formed in the substrate to define active structures. The field isolation structure includes a gap-fill pattern, a first material layer surrounding the gap-fill pattern, and a second material layer surrounding at least a portion of the first material layer. Each active structure includes a first active pattern having a top surface located beneath the level of the top surface of the field isolation structure, and a second active pattern disposed on the first active pattern and whose top is located above the level of the top surface of the field isolation structure.

    摘要翻译： 半导体存储器件包括具有掩埋在衬底中的沟道区和形成为提供低接触电阻的源极/漏极区的晶体管。 在衬底中形成场隔离结构以限定有源结构。 场隔离结构包括间隙填充图案，围绕间隙填充图案的第一材料层和围绕第一材料层的至少一部分的第二材料层。 每个有源结构包括第一有源图案，其具有位于场隔离结构的顶表面的平面下方的顶表面，以及布置在第一有源图案上的第二有源图案，其顶部位于第一有源图案的顶表面的高度之上 现场隔离结构。

    VERTICAL TYPE INTEGRATED CIRCUIT DEVICES, MEMORY DEVICES, AND METHODS OF FABRICATING THE SAME
    3.
    发明申请
    VERTICAL TYPE INTEGRATED CIRCUIT DEVICES, MEMORY DEVICES, AND METHODS OF FABRICATING THE SAME 有权
    垂直型集成电路装置，存储装置及其制造方法

    公开(公告)号：US20110095350A1

    公开(公告)日：2011-04-28

    申请号：US12891910

    申请日：2010-09-28

    申请人： Jae-man Yoon ,  Hyeong-sun Hong ,  Kwang-youl Chun ,  Makoto Yoshida ,  Deok-sung Hwang ,  Chul Lee

    发明人： Jae-man Yoon ,  Hyeong-sun Hong ,  Kwang-youl Chun ,  Makoto Yoshida ,  Deok-sung Hwang ,  Chul Lee

    IPC分类号： H01L27/108 ,  H01L29/78

    CPC分类号： H01L27/10897 ,  H01L27/105 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827

    摘要： A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.

    摘要翻译： 垂直型集成电路装置包括基板和从基板垂直突出的支柱。 支柱包括其中较低的杂质区域和上部杂质区域以及它们之间的垂直沟道区域。 包括其中较低杂质区域的柱的一部分包括从其横向延伸的台面。 该器件还包括在柱的第一侧壁上延伸并与下部杂质区电接触的第一导电线，以及在邻近垂直沟道区的柱的第二侧壁上延伸的第二导电线。 第二导电线在垂直于第一导电线的方向上延伸并且与台面间隔开。 还讨论了相关装置和制造方法。

    Trench-type capacitor, semiconductor device having the same, and semiconductor module having the semiconductor device
    4.
    发明授权
    Trench-type capacitor, semiconductor device having the same, and semiconductor module having the semiconductor device 有权
    沟槽型电容器，具有该沟槽型电容器的半导体器件和具有半导体器件的半导体模块

    公开(公告)号：US08502341B2

    公开(公告)日：2013-08-06

    申请号：US13021333

    申请日：2011-02-04

    申请人： Chul Lee ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

    发明人： Chul Lee ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

    IPC分类号： H01L29/92

    CPC分类号： H01L29/92

    摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.

    摘要翻译： 提供了沟槽型电容器。 为了形成电容器，第一和第二有源区域设置在半导体衬底中。 节点图案设置在第一活动区域中。 每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。 杂质扩散区域设置在节点图案附近。 设置与第一和第二有源区电接触的衬底连接图案。 与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。 此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

    METHOD OF FORMING SEMICONDUCTOR DEVICES WITH BURIED GATE ELECTRODES AND DEVICES FORMED BY THE SAME
    5.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICES WITH BURIED GATE ELECTRODES AND DEVICES FORMED BY THE SAME 审中-公开
    用铜基电极形成半导体器件的方法及其形成的器件

    公开(公告)号：US20120273791A1

    公开(公告)日：2012-11-01

    申请号：US13546296

    申请日：2012-07-11

    申请人： Bongsoo Kim ,  Chul Lee ,  Deoksung Hwang ,  Sang-Bin Ahn

    发明人： Bongsoo Kim ,  Chul Lee ,  Deoksung Hwang ,  Sang-Bin Ahn

    IPC分类号： H01L29/78

    CPC分类号： H01L29/4236 ,  H01L21/823437 ,  H01L29/66621 ,  H01L29/78

    摘要： A polycrystalline semiconductor layer is formed on a cell active region and a peripheral active region of a substrate. A buried gate electrode is formed in the substrate in the cell active region at a level below the polycrystalline semiconductor layer after forming the polycrystalline semiconductor layer. A gate electrode is formed on the substrate in the peripheral active region from the polysilicon semiconductor layer after forming the buried gate electrode.

    摘要翻译： 多晶半导体层形成在基板的单元有源区和周边有源区上。 在形成多晶半导体层之后，在多晶半导体层下方的电池有源区的基板中形成埋入栅电极。 在形成掩埋栅电极之后，在多晶硅半导体层的外围有源区的基板上形成栅电极。

    METHOD OF FORMING SEMICONDUCTOR DEVICES WITH BURIED GATE ELECTRODES AND DEVICES FORMED BY THE SAME
    6.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICES WITH BURIED GATE ELECTRODES AND DEVICES FORMED BY THE SAME 审中-公开
    用铜基电极形成半导体器件的方法及其形成的器件

    公开(公告)号：US20110171800A1

    公开(公告)日：2011-07-14

    申请号：US12944870

    申请日：2010-11-12

    申请人： Bongsoo Kim ,  Chul Lee ,  Deoksung Hwang ,  Sang-Bin Ahn

    发明人： Bongsoo Kim ,  Chul Lee ,  Deoksung Hwang ,  Sang-Bin Ahn

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4236 ,  H01L21/823437 ,  H01L29/66621 ,  H01L29/78

    摘要： A polycrystalline semiconductor layer is formed on a cell active region and a peripheral active region of a substrate. A buried gate electrode is formed in the substrate in the cell active region at a level below the polycrystalline semiconductor layer after forming the polycrystalline semiconductor layer. A gate electrode is formed on the substrate in the peripheral active region from the polysilicon semiconductor layer after forming the buried gate electrode.

    摘要翻译： 多晶半导体层形成在基板的单元有源区和周边有源区上。 在形成多晶半导体层之后，在多晶半导体层下方的电池有源区的基板中形成掩埋栅电极。 在形成掩埋栅电极之后，在多晶硅半导体层的外围有源区的基板上形成栅电极。

    HEALTH TRACKING SYSTEM WITH VERIFICATION OF NUTRITION INFORMATION
    7.
    发明公开
    HEALTH TRACKING SYSTEM WITH VERIFICATION OF NUTRITION INFORMATION 审中-公开

    公开(公告)号：US20230230671A1

    公开(公告)日：2023-07-20

    申请号：US17992424

    申请日：2022-11-22

    申请人： Chul Lee ,  Hesamoddin Salehian

    发明人： Chul Lee ,  Hesamoddin Salehian

    IPC分类号： G16H20/60 ,  G06F7/36 ,  G16H50/30 ,  G16H10/60

    CPC分类号： G16H20/60 ,  G06F7/36 ,  G16H50/30 ,  G16H10/60

    摘要： A method for decreasing a number of individual entries in a database of user-created records which describe a single item by: receiving a plurality of user-created records, each of said records comprising at least a descriptive string; placing individual ones of the plurality of user-created records having a sufficiently similar descriptive string into one of a plurality of first groups; hashing the descriptive string of each of the plurality of first groups in order to place two or more groups into a single bin; performing a pair-wise comparison of the descriptive strings of the two or more groups in each bin; and when the comparison of the descriptive strings of the two or more groups in a bin results in a distance below a first threshold, merging the two or more groups into a combined group.

    Recessed transistor and method of manufacturing the same
    8.
    发明授权
    Recessed transistor and method of manufacturing the same 有权
    嵌入式晶体管及其制造方法

    公开(公告)号：US09012982B2

    公开(公告)日：2015-04-21

    申请号：US12068179

    申请日：2008-02-04

    申请人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

    发明人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

    IPC分类号： H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66795 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7851

    摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

    摘要翻译： 提供凹陷晶体管及其制造方法。 凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。 衬底可以包括建立衬底的有源区和场区的隔离层。 衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。 有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。 栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。 源/漏区可以与有源区和栅电极相邻形成。