公开(公告)号：US08502341B2

公开(公告)日：2013-08-06

申请号：US13021333

申请日：2011-02-04

申请人： Chul Lee ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

发明人： Chul Lee ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

IPC分类号： H01L29/92

CPC分类号： H01L29/92

摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.

摘要翻译： 提供了沟槽型电容器。 为了形成电容器，第一和第二有源区域设置在半导体衬底中。 节点图案设置在第一活动区域中。 每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。 杂质扩散区域设置在节点图案附近。 设置与第一和第二有源区电接触的衬底连接图案。 与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。 此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

公开(公告)号：US20110210421A1

公开(公告)日：2011-09-01

申请号：US13021333

申请日：2011-02-04

申请人： CHUL LEE ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

发明人： CHUL LEE ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

IPC分类号： H01L29/92

CPC分类号： H01L29/92

摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.

摘要翻译： 提供了沟槽型电容器。 为了形成电容器，第一和第二有源区域设置在半导体衬底中。 节点图案设置在第一活动区域中。 每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。 杂质扩散区域设置在节点图案附近。 设置与第一和第二有源区电接触的衬底连接图案。 与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。 此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

公开(公告)号：US08872262B2

公开(公告)日：2014-10-28

申请号：US12781859

申请日：2010-05-18

申请人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

发明人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

IPC分类号： H01L27/108 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

摘要： Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

摘要翻译： 提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。 半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。 单元栅极图案设置在单元有源区和器件隔离层上。 外围栅极图案设置在外围有源区域上。 电池电节点设置在与电池栅极图案相邻的电池有源区域上。 外围电节点设置在与外围栅极图案相邻的外围有源区域上。 连接线设置在设置在器件隔离层上的单元栅极图案上。 连接线连接在单元栅极图案和外围栅极图案之间。

公开(公告)号：US07595529B2

公开(公告)日：2009-09-29

申请号：US12176263

申请日：2008-07-18

申请人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

发明人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

IPC分类号： H01L21/768

CPC分类号： H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

摘要： Provided are semiconductor integrated circuit (IC) devices having an upper pattern aligned with a lower pattern molded by a semiconductor substrate and methods of forming the same. In the semiconductor IC devices, the lower pattern contacts the upper pattern using an active region and/or an isolation layer. The methods include preparing a semiconductor substrate having an active region. A lower pattern is formed on the active region. The lower pattern is surrounded by the active region and protrudes from a top surface of the active region. An upper pattern is disposed on the lower pattern. The upper pattern contacts the lower pattern.

摘要翻译： 提供了具有与由半导体衬底模制的下部图案对准的上部图案的半导体集成电路（IC）器件及其形成方法。 在半导体IC器件中，下图案使用有源区和/或隔离层接触上图案。 所述方法包括制备具有活性区域的半导体衬底。 在有源区上形成较低的图案。 下图案被有源区域包围并从有源区域的顶表面突出。 上部图案设置在下部图案上。 上部图案接触下部图案。

公开(公告)号：US20100221875A1

公开(公告)日：2010-09-02

申请号：US12781859

申请日：2010-05-18

申请人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

发明人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

IPC分类号： H01L21/82

CPC分类号： H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

摘要： Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

摘要翻译： 提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。 半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。 单元栅极图案设置在单元有源区和器件隔离层上。 外围栅极图案设置在外围有源区域上。 电池电节点设置在与电池栅极图案相邻的电池有源区域上。 外围电节点设置在与外围栅极图案相邻的外围有源区域上。 连接线设置在设置在器件隔离层上的单元栅极图案上。 连接线连接在单元栅极图案和外围栅极图案之间。

公开(公告)号：US20080197393A1

公开(公告)日：2008-08-21

申请号：US11852940

申请日：2007-09-10

申请人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

发明人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

摘要： Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

摘要翻译： 提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。 半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。 单元栅极图案设置在单元有源区和器件隔离层上。 外围栅极图案设置在外围有源区域上。 电池电节点设置在与电池栅极图案相邻的电池有源区域上。 外围电节点设置在与外围栅极图案相邻的外围有源区域上。 连接线设置在设置在器件隔离层上的单元栅极图案上。 连接线连接在单元栅极图案和外围栅极图案之间。

公开(公告)号：US07745876B2

公开(公告)日：2010-06-29

申请号：US11852940

申请日：2007-09-10

申请人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

发明人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

IPC分类号： H01L27/108

CPC分类号： H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

摘要： Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

摘要翻译： 提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。 半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。 单元栅极图案设置在单元有源区和器件隔离层上。 外围栅极图案设置在外围有源区域上。 电池电节点设置在与电池栅极图案相邻的电池有源区域上。 外围电节点设置在与外围栅极图案相邻的外围有源区域上。 连接线设置在设置在器件隔离层上的单元栅极图案上。 连接线连接在单元栅极图案和外围栅极图案之间。

公开(公告)号：US07781285B2

公开(公告)日：2010-08-24

申请号：US11450936

申请日：2006-06-09

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US20100283094A1

公开(公告)日：2010-11-11

申请号：US12840599

申请日：2010-07-21

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US08174065B2

公开(公告)日：2012-05-08

申请号：US12840599

申请日：2010-07-21

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L29/66

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。