PAD AND METHOD FOR CHEMICAL MECHANICAL POLISHING
    1.
    发明申请
    PAD AND METHOD FOR CHEMICAL MECHANICAL POLISHING 审中-公开
    PAD和化学机械抛光方法

    公开(公告)号:US20120040532A1

    公开(公告)日:2012-02-16

    申请号:US13281162

    申请日:2011-10-25

    IPC分类号: H01L21/306

    CPC分类号: B24B37/24 B24D3/346

    摘要: A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.

    摘要翻译: 提供了半导体器件的两个相邻结构的化学机械抛光方法。 一种用于机械抛光的方法,包括:(a)提供半导体器件,其包括在其表面形成的凹部,形成在所述表面上的第一层,以及填充有所述凹部并形成在所述第一层上的第二层; 和(b)用垫和基本上无抑制剂的浆料基本上抛光第一层和第二层,其中该垫包括第二层的腐蚀抑制剂。

    METHOD FOR MERGING THE REGIONS IN THE IMAGE/VIDEO
    2.
    发明申请
    METHOD FOR MERGING THE REGIONS IN THE IMAGE/VIDEO 有权
    用于与图像/视频进行合并的方法

    公开(公告)号:US20120294516A1

    公开(公告)日:2012-11-22

    申请号:US13456286

    申请日:2012-04-26

    IPC分类号: G06K9/36

    摘要: The present invention relates to a method for merging regions in the image/video, capable of merging plural of image regions into an image merging region. In the disclosed method, these image regions are first sequenced basing on their compactness value. Then, one of these image regions is designated as a reference image region, and a merging test process is executed by merging the reference image region with one of the nearby image regions thereof in sequence, for forming a temporal image merging region. Later, the compactness value of the temporal image merging region is compared with the compactness value of the two consisting image regions thereof, respectively. When the compactness value of the temporal image merging region is larger than either one of the compactness value of the two consisting image regions thereof, the temporal image merging region is designated as an image merging region.

    摘要翻译: 本发明涉及一种用于合并图像/视频中的区域的方法,其能够将多个图像区域合并成图像合并区域。 在所公开的方法中,这些图像区域首先根据其紧凑度值进行测序。 然后,将这些图像区域中的一个指定为参考图像区域,并且通过依次将参考图像区域与其附近的图像区域中的一个合并来执行合并测试处理,以形成时间图像合成区域。 然后,将时间图像合成区域的紧凑度值分别与其组成的图像区域的紧凑度值进行比较。 当时间图像合并区域的紧凑度值大于其组成图像区域的两个的紧凑度值中的任一个时,时间图像合成区域被指定为图像合并区域。

    METHOD AND APPARATUS FOR IMPROVED MULTIPLEXING USING TRI-STATE INVERTER
    3.
    发明申请
    METHOD AND APPARATUS FOR IMPROVED MULTIPLEXING USING TRI-STATE INVERTER 有权
    使用三态逆变器改进多路复用的方法和装置

    公开(公告)号:US20130113520A1

    公开(公告)日:2013-05-09

    申请号:US13291204

    申请日:2011-11-08

    IPC分类号: H03K19/02 H05K3/30

    摘要: A multiplexing circuit includes first and second tri-state inverters coupled to first and second data input nodes, respectively. The first and second tri-state inverters include first and second stacks of transistors, respectively, coupled between power supply and ground nodes. Each stack includes first and second PMOS transistors and first and second NMOS transistors. The first and second stacks include first and second dummy transistors, respectively.

    摘要翻译: 复用电路包括分别耦合到第一和第二数据输入节点的第一和第二三态反相器。 第一和第二三态反相器分别包括耦合在电源和接地节点之间的第一和第二晶体管堆叠。 每个堆叠包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管。 第一和第二堆叠分别包括第一和第二虚拟晶体管。

    ANTENNA CELL DESIGN TO PREVENT PLASMA INDUCED GATE DIELECTRIC DAMAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS
    4.
    发明申请
    ANTENNA CELL DESIGN TO PREVENT PLASMA INDUCED GATE DIELECTRIC DAMAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS 有权
    天线细胞设计,以防止半导体集成电路中的等离子体感应栅电介质损伤

    公开(公告)号:US20130146981A1

    公开(公告)日:2013-06-13

    申请号:US13316807

    申请日:2011-12-12

    IPC分类号: H01L27/088 H01L21/283

    摘要: An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.

    摘要翻译: 提供了一种用于防止等离子体增强的栅极介质故障的天线单元。 天线单元设计利用多晶硅引线作为虚拟晶体管的栅极。 多晶硅引线可以是一组并联的嵌套多晶硅引线之一。 虚拟晶体管包括连接到保持在VSS处的衬底的栅极,直接通过金属引线或间接地通过连接低电池连接。 栅极设置在设置在连续源极/漏极区域上的电介质上,其中源极和漏极连接在一起。 二极管与形成有半导体衬底的半导体衬底形成。 源极/漏极区域耦合到另一个金属引线,金属引线可以是输入引脚并且耦合到有源晶体管栅极,防止等离子体对有源晶体管的栅极介电损伤。

    METHOD FOR DEPTH MAP GENERATION
    5.
    发明申请
    METHOD FOR DEPTH MAP GENERATION 有权
    深度地图生成方法

    公开(公告)号:US20120293499A1

    公开(公告)日:2012-11-22

    申请号:US13456280

    申请日:2012-04-26

    IPC分类号: G06T15/00

    摘要: A method for depth map generation is disclosed, capable of generating a depth map corresponding an image signal, for the application of a 2D to 3D image transformation system. In the depth map generated by the disclosed method, each of the plural image regions of the image signal is assigned with a depth value. Besides, by means of comparing the depth map with another depth map of the earlier time point, the disclosed method can generate a modulated depth map, for assigning a depth value to each of the plural image regions of the image signal more precisely. Thus, the transformation performance and efficiency of the 2D to 3D image transformation system are hereby improved.

    摘要翻译: 公开了一种用于深度图生成的方法,能够生成对应于图像信号的深度图,以应用2D到3D图像变换系统。 在通过所公开的方法生成的深度图中,将图像信号的多个图像区域中的每一个分配给深度值。 此外,通过将深度图与较早时间点的另一深度图进行比较,所公开的方法可以生成调制深度图,用于更准确地为图像信号的多个图像区域中的每一个分配深度值。 因此,改善了2D到3D图像变换系统的变换性能和效率。