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公开(公告)号：US09337290B2
公开(公告)日：2016-05-10
申请号：US13537804
申请日：2012-06-29
申请人： Lee-Chung Lu , Li-Chun Tien , Hui-Zhong Zhuang
发明人： Lee-Chung Lu , Li-Chun Tien , Hui-Zhong Zhuang
IPC分类号： H01L29/423 , H01L29/417 , H01L27/32 , H01L27/02 , H01L21/768
CPC分类号： H01L21/823475 , H01L21/32055 , H01L21/76802 , H01L21/76895 , H01L21/823418 , H01L27/0207 , H01L27/326 , H01L29/0649 , H01L29/41725 , H01L29/41775 , H01L29/4238
摘要： An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact.
摘要翻译： 提供集成电路。 集成电路包括设置在第一源极/漏极区域上的第一触点，设置在第二源极/漏极区域上的第二触点，设置在栅极上的多晶硅，插入在第一触点和第二触点之间的多晶硅，第一多晶硅 在有源区内桥接多晶硅和第一接触，以及电耦合到第一多晶硅接触的输出结构。
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2.发明授权Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits 有权天线电池设计，以防止半导体集成电路中的等离子体感应栅介质损坏公开(公告)号：US08872269B2
公开(公告)日：2014-10-28
申请号：US13316807
申请日：2011-12-12
申请人： Jen-Hang Yang , Chun-Fu Chen , Pin-Dai Sue , Hui-Zhong Zhuang
发明人： Jen-Hang Yang , Chun-Fu Chen , Pin-Dai Sue , Hui-Zhong Zhuang
IPC分类号： H01L21/70
CPC分类号： H01L21/28008 , H01L21/283 , H01L21/76895 , H01L23/60 , H01L27/0207 , H01L27/0629 , H01L27/0811 , H01L2924/0002 , H01L2924/00
摘要： An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.
摘要翻译： 提供了一种用于防止等离子体增强的栅极介质故障的天线单元。 天线单元设计利用多晶硅引线作为虚拟晶体管的栅极。 多晶硅引线可以是一组并联的嵌套多晶硅引线之一。 虚拟晶体管包括连接到保持在VSS处的衬底的栅极，直接通过金属引线或间接地通过连接低电池连接。 栅极设置在设置在连续源极/漏极区域上的电介质上，其中源极和漏极连接在一起。 二极管与形成有半导体衬底的半导体衬底形成。 源极/漏极区域耦合到另一个金属引线，金属引线可以是输入引脚并且耦合到有源晶体管栅极，防止等离子体对有源晶体管的栅极介电损伤。
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3.发明申请公开(公告)号：US20130113520A1
公开(公告)日：2013-05-09
申请号：US13291204
申请日：2011-11-08
申请人： Chun-Fu CHEN , Hui-Zhong Zhuang , Jen-Hang Yang
发明人： Chun-Fu CHEN , Hui-Zhong Zhuang , Jen-Hang Yang
CPC分类号： H03K19/1737 , H01L27/0207 , Y10T29/4913
摘要： A multiplexing circuit includes first and second tri-state inverters coupled to first and second data input nodes, respectively. The first and second tri-state inverters include first and second stacks of transistors, respectively, coupled between power supply and ground nodes. Each stack includes first and second PMOS transistors and first and second NMOS transistors. The first and second stacks include first and second dummy transistors, respectively.
摘要翻译： 复用电路包括分别耦合到第一和第二数据输入节点的第一和第二三态反相器。 第一和第二三态反相器分别包括耦合在电源和接地节点之间的第一和第二晶体管堆叠。 每个堆叠包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管。 第一和第二堆叠分别包括第一和第二虚拟晶体管。
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公开(公告)号：US20130087932A1
公开(公告)日：2013-04-11
申请号：US13267310
申请日：2011-10-06
申请人： Lee-Chung LU , Li-Chun TIEN , Hui-Zhong ZHUANG , Mei-Hui HUANG
发明人： Lee-Chung LU , Li-Chun TIEN , Hui-Zhong ZHUANG , Mei-Hui HUANG
CPC分类号： H01L27/0207 , G06F17/5068 , G06F17/5077 , H01L27/11807 , H01L2027/11875 , H01L2027/11885
摘要： A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell.
摘要翻译： 设计集成电路的方法包括在第一标准单元中部署有效区域。 至少一个栅电极被路由，与第一标准单元中的有效区重叠。 至少一个金属线结构被路由，与第一标准单元中的有效区重叠。 至少一个金属线结构基本上平行于栅电极。 第一电源轨道基本上正交于第一标准单元中的至少一个金属线结构。 第一电力轨与至少一个金属线结构重叠。 第一动力轨具有与至少一个金属线结构相邻的平坦边缘。 第一连接插头部署在第一电力轨道与第一标准单元中的至少一个金属线结构重叠的区域处。
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公开(公告)号：US20140001595A1
公开(公告)日：2014-01-02
申请号：US13537804
申请日：2012-06-29
申请人： Lee-Chung Lu , Li-Chun Tien , Hui-Zhong Zhuang
发明人： Lee-Chung Lu , Li-Chun Tien , Hui-Zhong Zhuang
CPC分类号： H01L21/823475 , H01L21/32055 , H01L21/76802 , H01L21/76895 , H01L21/823418 , H01L27/0207 , H01L27/326 , H01L29/0649 , H01L29/41725 , H01L29/41775 , H01L29/4238
摘要： An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact.
摘要翻译： 提供集成电路。 集成电路包括设置在第一源极/漏极区域上的第一触点，设置在第二源极/漏极区域上的第二触点，设置在栅极上的多晶硅，插入在第一触点和第二触点之间的多晶硅，第一多晶硅 在有源区内桥接多晶硅和第一接触，以及电耦合到第一多晶硅接触的输出结构。
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公开(公告)号：US08607172B2
公开(公告)日：2013-12-10
申请号：US13267310
申请日：2011-10-06
申请人： Lee-Chung Lu , Li-Chun Tien , Hui-Zhong Zhuang , Mei-Hui Huang
发明人： Lee-Chung Lu , Li-Chun Tien , Hui-Zhong Zhuang , Mei-Hui Huang
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5068 , G06F17/5077 , H01L27/11807 , H01L2027/11875 , H01L2027/11885
摘要： A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell.
摘要翻译： 设计集成电路的方法包括在第一标准单元中部署有效区域。 至少一个栅电极被路由，与第一标准单元中的有效区重叠。 至少一个金属线结构被路由，与第一标准单元中的有效区重叠。 至少一个金属线结构基本上平行于栅电极。 第一电源轨道基本上正交于第一标准单元中的至少一个金属线结构。 第一电力轨与至少一个金属线结构重叠。 第一动力轨具有与至少一个金属线结构相邻的平坦边缘。 第一连接插头部署在第一电力轨道与第一标准单元中的至少一个金属线结构重叠的区域处。
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7.发明申请ANTENNA CELL DESIGN TO PREVENT PLASMA INDUCED GATE DIELECTRIC DAMAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS 有权天线细胞设计，以防止半导体集成电路中的等离子体感应栅电介质损伤公开(公告)号：US20130146981A1
公开(公告)日：2013-06-13
申请号：US13316807
申请日：2011-12-12
申请人： Jen-Hang YANG , Chun-Fu CHEN , Pin-Dai SUE , Hui-Zhong ZHUANG
发明人： Jen-Hang YANG , Chun-Fu CHEN , Pin-Dai SUE , Hui-Zhong ZHUANG
IPC分类号： H01L27/088 , H01L21/283
CPC分类号： H01L21/28008 , H01L21/283 , H01L21/76895 , H01L23/60 , H01L27/0207 , H01L27/0629 , H01L27/0811 , H01L2924/0002 , H01L2924/00
摘要： An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.
摘要翻译： 提供了一种用于防止等离子体增强的栅极介质故障的天线单元。 天线单元设计利用多晶硅引线作为虚拟晶体管的栅极。 多晶硅引线可以是一组并联的嵌套多晶硅引线之一。 虚拟晶体管包括连接到保持在VSS处的衬底的栅极，直接通过金属引线或间接地通过连接低电池连接。 栅极设置在设置在连续源极/漏极区域上的电介质上，其中源极和漏极连接在一起。 二极管与形成有半导体衬底的半导体衬底形成。 源极/漏极区域耦合到另一个金属引线，金属引线可以是输入引脚并且耦合到有源晶体管栅极，防止等离子体对有源晶体管的栅极介电损伤。
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8.发明授权公开(公告)号：US08482314B2
公开(公告)日：2013-07-09
申请号：US13291204
申请日：2011-11-08
申请人： Chun-Fu Chen , Hui-Zhong Zhuang , Jen-Hang Yang
发明人： Chun-Fu Chen , Hui-Zhong Zhuang , Jen-Hang Yang
IPC分类号： H03K19/00
CPC分类号： H03K19/1737 , H01L27/0207 , Y10T29/4913
摘要： A multiplexing circuit includes first and second tri-state inverters coupled to first and second data input nodes, respectively. The first and second tri-state inverters include first and second stacks of transistors, respectively, coupled between power supply and ground nodes. Each stack includes first and second PMOS transistors and first and second NMOS transistors. The first and second stacks include first and second dummy transistors, respectively.
摘要翻译： 复用电路包括分别耦合到第一和第二数据输入节点的第一和第二三态反相器。 第一和第二三态反相器分别包括耦合在电源和接地节点之间的第一和第二晶体管堆叠。 每个堆叠包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管。 第一和第二堆叠分别包括第一和第二虚拟晶体管。
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