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    Memory device and methods for its fabrication
    1.
    发明授权
    Memory device and methods for its fabrication 有权
    存储器件及其制造方法

    公开(公告)号：US07432156B1

    公开(公告)日：2008-10-07

    申请号：US11409361

    申请日：2006-04-20

    申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

    发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

    IPC分类号： H01L21/8247

    CPC分类号： H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

    摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

    摘要翻译： 提供半导体存储器件及其制造方法。 根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。 蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。 掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

    Memory device and methods for its fabrication
    2.
    发明授权
    Memory device and methods for its fabrication 有权
    存储器件及其制造方法

    公开(公告)号：US07564091B2

    公开(公告)日：2009-07-21

    申请号：US12199692

    申请日：2008-08-27

    申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

    发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

    摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

    摘要翻译： 提供半导体存储器件及其制造方法。 根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。 蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。 掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

    MEMORY DEVICE AND METHODS FOR ITS FABRICATION
    3.
    发明申请
    MEMORY DEVICE AND METHODS FOR ITS FABRICATION 有权
    存储器件及其制造方法

    公开(公告)号：US20080315290A1

    公开(公告)日：2008-12-25

    申请号：US12199692

    申请日：2008-08-27

    申请人： Chungho LEE ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

    发明人： Chungho LEE ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

    IPC分类号： H01L29/00

    CPC分类号： H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

    摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

    摘要翻译： 提供半导体存储器件及其制造方法。 根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。 蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。 掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

    Methods for fabricating a split charge storage node semiconductor memory
    4.
    发明授权
    Methods for fabricating a split charge storage node semiconductor memory 有权
    分离电荷存储节点半导体存储器的制造方法

    公开(公告)号：US07666739B2

    公开(公告)日：2010-02-23

    申请号：US11614048

    申请日：2006-12-20

    申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

    发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28282 ,  H01L29/792

    摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

    摘要翻译： 提供了用于制造分离电荷存储节点半导体存储器件的方法。 根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极 。 栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。 第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构 厚度。

    Semiconductor memory comprising dual charge storage nodes and methods for its fabrication
    5.
    发明授权
    Semiconductor memory comprising dual charge storage nodes and methods for its fabrication 有权
    半导体存储器包括双电荷存储节点及其制造方法

    公开(公告)号：US08076712B2

    公开(公告)日：2011-12-13

    申请号：US12840165

    申请日：2010-07-20

    申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

    发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

    摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

    摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且第二层结构形成在第二侧上，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

    Semiconductor memory comprising dual charge storage nodes and methods for its fabrication
    6.
    发明授权
    Semiconductor memory comprising dual charge storage nodes and methods for its fabrication 有权
    半导体存储器包括双电荷存储节点及其制造方法

    公开(公告)号：US07767517B2

    公开(公告)日：2010-08-03

    申请号：US11613513

    申请日：2006-12-20

    申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

    发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

    摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

    摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

    METHODS FOR FABRICATING A SPLIT CHARGE STORAGE NODE SEMICONDUCTOR MEMORY
    7.
    发明申请
    METHODS FOR FABRICATING A SPLIT CHARGE STORAGE NODE SEMICONDUCTOR MEMORY 有权
    用于制造分离充电储存节点半导体存储器的方法

    公开(公告)号：US20080153222A1

    公开(公告)日：2008-06-26

    申请号：US11614048

    申请日：2006-12-20

    申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

    发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28282 ,  H01L29/792

    摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

    摘要翻译： 提供了用于制造分离电荷存储节点半导体存储器件的方法。 根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极 。 栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。 第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构 厚度。

    SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION
    8.
    发明申请
    SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION 有权
    包含双电池存储器的半导体存储器及其制造方法

    公开(公告)号：US20080149999A1

    公开(公告)日：2008-06-26

    申请号：US11613513

    申请日：2006-12-20

    申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

    发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

    摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

    摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

    Programming in memory devices using source bitline voltage bias
    10.
    发明授权
    Programming in memory devices using source bitline voltage bias 有权
    使用源位线电压偏置对存储器件进行编程

    公开(公告)号：US07746698B2

    公开(公告)日：2010-06-29

    申请号：US11956032

    申请日：2007-12-13

    申请人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

    发明人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0491 ,  G11C16/12

    摘要： Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

    摘要翻译： 提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。 优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。 优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流， 导致功率有效的编程和改进的编程速度。