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    PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS
    1.
    发明申请
    PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS 有权
    使用源电压偏置在存储器件中编程

    公开(公告)号：US20090154246A1

    公开(公告)日：2009-06-18

    申请号：US11956032

    申请日：2007-12-13

    申请人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

    发明人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0491 ,  G11C16/12

    摘要： Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

    摘要翻译： 提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。 优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。 优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流， 导致功率有效的编程和改进的编程速度。

    Programming in memory devices using source bitline voltage bias
    2.
    发明授权
    Programming in memory devices using source bitline voltage bias 有权
    使用源位线电压偏置对存储器件进行编程

    公开(公告)号：US07746698B2

    公开(公告)日：2010-06-29

    申请号：US11956032

    申请日：2007-12-13

    申请人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

    发明人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0491 ,  G11C16/12

    摘要： Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

    摘要翻译： 提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。 优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。 优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流， 导致功率有效的编程和改进的编程速度。

    DEVICE AND PROCESS OF FORMING DEVICE WITH PRE-PATTERNED TRENCH AND GRAPHENE-BASED DEVICE STRUCTURE FORMED THEREIN
    4.
    发明申请
    DEVICE AND PROCESS OF FORMING DEVICE WITH PRE-PATTERNED TRENCH AND GRAPHENE-BASED DEVICE STRUCTURE FORMED THEREIN 有权
    具有预先形成的TRENCH和基于石墨的器件结构形成器件的器件和工艺

    公开(公告)号：US20100051960A1

    公开(公告)日：2010-03-04

    申请号：US12201851

    申请日：2008-08-29

    申请人： An Chen ,  Zoran Krivokapic

    发明人： An Chen ,  Zoran Krivokapic

    IPC分类号： H01L29/16 ,  H01L21/04

    CPC分类号： H01L29/78684 ,  H01L29/1606 ,  H01L29/66742 ,  H01L29/7781

    摘要： A graphene-based device is formed with a trench in one or more layers of material, a graphene layer within the trench, and a device structure on the graphene layer and within the trench. Fabrication techniques includes forming a trench defined by one or more layers of material, forming a graphene layer within the trench, and forming a device structure on the graphene layer and within the trench.

    摘要翻译： 基于石墨烯的器件形成有一层或多层材料中的沟槽，沟槽内的石墨烯层，以及石墨烯层和沟槽内的器件结构。 制造技术包括形成由一层或多层材料限定的沟槽，在沟槽内形成石墨烯层，并在石墨烯层和沟槽内形成器件结构。

    BANDGAP REFERENCE CIRCUIT
    6.
    发明申请
    BANDGAP REFERENCE CIRCUIT 有权
    带宽参考电路

    公开(公告)号：US20080018317A1

    公开(公告)日：2008-01-24

    申请号：US11781904

    申请日：2007-07-23

    申请人： An Chen ,  Hung-Cheng Huang ,  Wen-Lung Cheng ,  Ming-Tse Lin

    发明人： An Chen ,  Hung-Cheng Huang ,  Wen-Lung Cheng ,  Ming-Tse Lin

    IPC分类号： G05F3/16 ,  G05F3/20

    CPC分类号： G05F3/30

    摘要： A bandgap reference circuit having a low sensitivity to temperature and supplied voltage installs a compensation circuit on a bandgap reference circuit to substitute a prior art that uses a resistor to match the circuit startup purpose and solve the problem of startup error caused by the manufacturing error. The bandgap reference circuit includes a first amplifier, a second amplifier, and a reference circuit having a plurality of transistors and a plurality of bipolar junction transistors, and the bandgap reference circuit is electrically connected to a same supplied power of which the reference circuit is electrically connected and also includes a plurality of transistors and a compensation circuit of the second amplifier, so as to output a stable startup voltage which has a low sensitivity to the change of temperature and the change of supplied voltage.

    摘要翻译： 具有低温敏感性和供电电压的带隙基准电路将补偿电路安装在带隙参考电路上以替代使用电阻器的现有技术来匹配电路启动目的，并解决由制造误差引起的启动误差的问题。 带隙参考电路包括第一放大器，第二放大器和具有多个晶体管和多个双极结型晶体管的参考电路，并且带隙基准电路电连接到与基准电路电连接的相同供电电力 并且还包括多个晶体管和第二放大器的补偿电路，以便输出对温度变化和供电电压变化具有低灵敏度的稳定启动电压。

    Surface passivation for III-V compound semiconductors
    8.
    发明申请
    Surface passivation for III-V compound semiconductors 审中-公开
    III-V化合物半导体的表面钝化

    公开(公告)号：US20060145190A1

    公开(公告)日：2006-07-06

    申请号：US11323882

    申请日：2005-12-30

    申请人： David Salzman ,  Aristo Yulius ,  An Chen ,  Jerry Woodall ,  Eric Harmon

    发明人： David Salzman ,  Aristo Yulius ,  An Chen ,  Jerry Woodall ,  Eric Harmon

    IPC分类号： H01L31/0328

    CPC分类号： H01L29/66462 ,  H01L21/28264 ,  H01L31/0735 ,  H01L31/1868 ,  Y02E10/544

    摘要： A structure and method of fabrication are disclosed for improving surface passivation of III-V compound semiconductors. The invention exploits certain anion-rich compound semiconductors to form a high quality interface with a dielectric when anion mobility is increased during an annealing step. Low post-annealing surface state densities result in a low fixed charge density at the interface and low surface recombination velocities. The invention enables microelectronic devices including diode, transistor, solar cell, photodetector, and CCDs with superior performance wherever prior art devices have inferior surface passivation.

    摘要翻译： 公开了一种用于改善III-V族化合物半导体的表面钝化的结构和制造方法。 当退火步骤中阴离子迁移率增加时，本发明利用某些富含阴离子的化合物半导体形成具有电介质的高质量界面。 低退火表面状态密度导致界面处固定电荷密度低，表面复合速度低。 本发明使得包括二极管，晶体管，太阳能电池，光电检测器和CCD的微电子器件在现有技术的器件具有较差的表面钝化的情况下具有优异的性能。