-
公开(公告)号：US11245370B2
公开(公告)日：2022-02-08
申请号：US17002270
申请日：2020-08-25
Inventor： Zhaohui He , Ruoxin Jiang , Rahul Singh
Abstract: A Class-D amplifier includes a plurality of power rails, a quantizer, and a driver stage. The quantizer and the driver stage have a combined gain. For each power rail of the plurality of power rails, the Class-D amplifier senses a voltage value for the power rail and determines a ramp amplitude based on the sensed voltage value. The Class-D amplifier concurrently switches from the driver stage using a first power rail to a second power rail of the plurality of power rails and switches from the quantizer using the ramp amplitude associated with the first power rail to using the ramp amplitude associated with the second power rail so that the combined gain is constant.
-
公开(公告)号：US10862442B2
公开(公告)日：2020-12-08
申请号：US16184909
申请日：2018-11-08
Inventor： Zhaohui He , Rahul Singh , Ruoxin Jiang
Abstract: In a Class-D amplifier, first/second ratios and first/second RC time constants are sequentially matched by trimming. An integrator is coupled to differential first/second paths. The first/second ratios are of a feedback resistor to an input resistor in the first/second paths. R's of the first/second RC time constants are the resistors of the first/second matched ratios. C's of the first/second RC time constants are integrating capacitors in the first/second path. For each of multiple power rails, a ramp amplitude is determined based on a sensed voltage. Concurrently, the driver stage is switched from first to second power rails and quantizer switched from first to second ramp amplitudes to achieve constant combined quantizer/driver stage gain. Based on a sensed load current, an IR drop is determined for a respective output impedance of the driver stage and added to a loop filter output to compensate for the respective output impedance.
-
公开(公告)号：US09973156B2
公开(公告)日：2018-05-15
申请号：US15285038
申请日：2016-10-04
Inventor： Eric J. King , Zhaohui He , John L. Melanson , Siddharth Maru
CPC classification number: H03F3/2171 , H02M5/293 , H02M2005/2932 , H03F1/0216 , H03F1/0227 , H03F1/32 , H03F3/185 , H03F3/2173 , H03F3/2178 , H03F2200/03 , H03F2200/153 , H03F2200/432 , H04R3/12
Abstract: A method may include processing a first signal derived from an input signal with a first path to generate a first path voltage at a first path output, processing a second signal derived from the input signal with a second path to generate a second path voltage at a second path output, the second path comprising a linear amplifier having at least one transistor for driving the second path voltage, generating the first signal and the second signal with a signal splitter, such that the second signal comprises information of the input signal absent from the first signal, and such that the second path voltage is of a sufficient magnitude such that the at least one transistor operates in a saturation region of the at least one transistor throughout a dynamic range of a load voltage equal to the difference of the first path voltage and the second path voltage.
-
公开(公告)号：US20210044264A1
公开(公告)日：2021-02-11
申请号：US17002270
申请日：2020-08-25
Inventor： Zhaohui He , Ruoxin Jiang , Rahul Singh
Abstract: A Class-D amplifier includes a plurality of power rails, a quantizer, and a driver stage. The quantizer and the driver stage have a combined gain. For each power rail of the plurality of power rails, the Class-D amplifier senses a voltage value for the power rail and determines a ramp amplitude based on the sensed voltage value. The Class-D amplifier concurrently switches from the driver stage using a first power rail to a second power rail of the plurality of power rails and switches from the quantizer using the ramp amplitude associated with the first power rail to using the ramp amplitude associated with the second power rail so that the combined gain is constant.
-
公开(公告)号：US10476455B1
公开(公告)日：2019-11-12
申请号：US16057820
申请日：2018-08-08
Inventor： Paul Astrachan , Emmanuel Marchais , Lingli Zhang , Zhaohui He , Kyehyung Lee , Tejasvi Das , John L. Melanson
Abstract: A class-D amplifier system includes one or more pulse width modulation (PWM) output paths at least one of which includes one or more digital closed-loop PWM modulators (DCL-PWMM) in which at least one of the DCL_PWMM includes a digital integrator that provides an output value and receives a feedback value. The output value has an output resolution and the feedback value has a feedback resolution that is coarser than the output resolution. The output value is the sum of an integer multiple of the feedback resolution and a residue. Control logic decreases/increases the residue of the digital integrator toward an integer multiple of the feedback resolution over a plurality of clock cycles in response to a request to transition the class-D amplifier and forces an output of the DCL_PWMM to have an approximate 50% duty cycle after decreasing/increasing the residue over the plurality of clock cycles.
-
Patent Agency Ranking
公开(公告)号：US20210044265A1
公开(公告)日：2021-02-11
申请号：US17002315
申请日：2020-08-25
Inventor： Zhaohui He , Ruoxin Jiang , Rahul Singh
Abstract: A Class-D amplifier that includes a driver stage operable in a plurality of modes having different respective output impedances, a loop filter having an output, and a circuit configured to sense a current at a load of the Class-D amplifier, determine, based on the sensed current, an IR drop for a respective output impedance of the driver stage, and add the IR drop to the loop filter output to compensate for the respective output impedance of the driver stage to reduce distortion.
-
公开(公告)号：US09906196B2
公开(公告)日：2018-02-27
申请号：US15270631
申请日：2016-09-20
Inventor： Zhaohui He , Eric J. King , Siddharth Maru , John L. Melanson
CPC classification number: H03F3/217 , H03F1/04 , H03F1/34 , H03F3/185 , H03F3/2171 , H03F3/2173 , H03F3/45475 , H03F2200/351 , H03F2200/432 , H03F2203/45034 , H04R3/12 , H04R2420/03
Abstract: A switching power stage for producing a load voltage may include a first processing path having a first output, a second processing path having a second output, a first plurality of switches comprising at least a first switch coupled between the first output and a first load terminal and a second switch coupled between the first output and the second load terminal, a second plurality of switches comprising at least a third switch coupled between the second output and the first load terminal and a fourth switch coupled between the second output and the second load terminal, and a controller configured to control switches in order to generate the load voltage as a function of an input signal such that one of the first switch and the second switch operates in a linear region of operation and one of the third switch and the fourth switch operates in a saturated region of operation for a predominance of a dynamic rage of the load voltage.
-
公开(公告)号：US11290069B2
公开(公告)日：2022-03-29
申请号：US17002315
申请日：2020-08-25
Inventor： Zhaohui He , Ruoxin Jiang , Rahul Singh
Abstract: A Class-D amplifier that includes a driver stage operable in a plurality of modes having different respective output impedances, a loop filter having an output, and a circuit configured to sense a current at a load of the Class-D amplifier, determine, based on the sensed current, an IR drop for a respective output impedance of the driver stage, and add the IR drop to the loop filter output to compensate for the respective output impedance of the driver stage to reduce distortion.
-
公开(公告)号：US10090814B2
公开(公告)日：2018-10-02
申请号：US15270687
申请日：2016-09-20
Inventor： John L. Melanson , Eric J. King , Zhaohui He , Siddharth Maru
Abstract: A signal processing system for producing a load voltage at a load output of the signal processing system, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, and may include a first processing path configured to process a first signal derived from an input signal to generate the first load voltage at a first processing path output, a second processing path configured to process a second signal received at a second processing path input and derived from the input signal, wherein the second signal comprises information of the input signal absent from the first signal, to generate the second load voltage at a second processing path output, and a high-pass filter coupled between the first processing path output and the second processing path input.
-
公开(公告)号：US10972061B2
公开(公告)日：2021-04-06
申请号：US16184511
申请日：2018-11-08
Inventor： Zhaohui He , Rahul Singh , Ruoxin Jiang
Abstract: A Class-D amplifier having a low power dissipation mode includes first and second independent output stages that receive respective first and second level power supply voltages for driving a load coupled to the amplifier output during respective first and second operating modes. Bypass switches are controllable to disconnect the second output stage from the output during the first operating mode and to connect the second output stage to the output during the second operating mode. The operating modes are selected based on the amplifier output power level. First and second independent pre-driver stages receive the respective first and second level power supply voltages for driving the respective first and second independent output stages. During the second operating mode the first pre-driver stage is placed into a low power dissipation state and during the first operating mode the second pre-driver stage is placed into a low power dissipation state.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.014 seconds)
