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公开(公告)号：US6060919A
公开(公告)日：2000-05-09
申请号：US205033
申请日：1998-12-04
申请人： Dennis R. Wilson , William F. Kraus
发明人： Dennis R. Wilson , William F. Kraus
CPC分类号： H03K3/356104 , H03K3/356008
摘要： A preferred state power-up latch circuit includes first and second cross-coupled P-channel transistors coupled to a first source of supply voltage, first and second cross-coupled N-channel transistors coupled to a second source of supply voltage, the transistors being coupled together to form a latch having an output node, in which at least one of the gate lengths is unequal to the other gates lengths in order to establish a preferred state upon power-up, and the gate width of all the transistors is equal.
摘要翻译： 优选的状态上电锁存电路包括耦合到第一电源电压源的第一和第二交叉耦合P沟道晶体管，耦合到第二电源电压源的第一和第二交叉耦合N沟道晶体管，晶体管是 耦合在一起以形成具有输出节点的锁存器，其中至少一个栅极长度与其他栅极长度不相等，以便在上电时建立优选状态，并且所有晶体管的栅极宽度相等。
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公开(公告)号：US5774392A
公开(公告)日：1998-06-30
申请号：US620799
申请日：1996-03-28
申请人： William F. Kraus , Dennis R. Wilson
发明人： William F. Kraus , Dennis R. Wilson
CPC分类号： G11C11/22
摘要： A ferroelectric memory array includes a word line coupled to a row of ferroelectric memory cells and a word line driver circuit for establishing a full power supply voltage on the word line. A bootstrapping circuit is coupled between the word line and a boost line for receiving a boost signal. The bootstrapping circuit includes a ferroelectric capacitor and coupling circuitry for coupling the ferroelectric capacitor between the boost line and the word line in a first operational mode such that the peak voltage on the word line is greater than the power supply voltage, and for isolating the ferroelectric capacitor from the boost line in a second operational mode. In operation, a selected word line is precharged to a full VDD power supply voltage, the ferroelectric capacitor associated with the selected word line is coupled to the boost line, the ferroelectric capacitors associated with non-selected word lines are electrically isolated from the boost line, and the boost line transitions from zero volts to VDD such that the voltage on the selected word line is boosted to a voltage greater than the VDD power supply voltage.
摘要翻译： 铁电存储器阵列包括耦合到一排铁电存储器单元的字线和用于在字线上建立全电源电压的字线驱动器电路。 自举电路耦合在字线和用于接收升压信号的升压线之间。 自举电路包括铁电电容器和耦合电路，其用于在第一操作模式下在升压线和字线之间耦合铁电电容器，使得字线上的峰值电压大于电源电压，并且用于隔离铁电 电容器从升压线在第二操作模式。 在操作中，选择的字线被预充电到一个完整的VDD电源电压，与所选字线相关联的铁电电容器耦合到升压线，与非选择的字线相关联的铁电电容器与升压线电隔离 ，并且升压线从零伏特转变为VDD，使得所选择的字线上的电压升高到大于VDD电源电压的电压。
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公开(公告)号：US5986919A
公开(公告)日：1999-11-16
申请号：US970518
申请日：1997-11-14
IPC分类号： G11C11/22 , H01L27/108 , H01L27/115 , G11C7/00
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/10897 , H01L27/108
摘要： A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.
摘要翻译： 用于1T / 1C铁电存储器阵列的参考单元布局包括具有耦合到参考字线的栅极和耦合在位线和内部单元节点之间的电流通路的第一极性类型的晶体管， 具有耦合到预充电线的栅极和耦合在电源电压源和内部单元节点之间的电流路径的第二极性类型，跨越参考电池延伸的分流参考字线，其与参考字线电隔离 ，预充电线和存储单元的物理边界内的晶体管，以及耦合在内部单元节点和参考板线之间的铁电电容器。
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公开(公告)号：US5880989A
公开(公告)日：1999-03-09
申请号：US970453
申请日：1997-11-14
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , G11C7/00
CPC分类号： G11C11/22
摘要： A method of operating a 1T/1C ferroelectric memory having a memory cell coupled to a word line, a bit line, and a plate line, includes the steps of turning on the word line, energizing the plate line to establish a charge on the bit line, turning off the word line, and sensing the charge on the bit line while the word line is off.
摘要翻译： 一种操作具有耦合到字线，位线和板线的存储单元的1T / 1C铁电存储器的方法包括以下步骤：打开字线，激励板线以在该位上建立电荷 线，关闭字线，并在字线关闭时感测位线上的电荷。
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公开(公告)号：US06252793B1
公开(公告)日：2001-06-26
申请号：US09663121
申请日：2000-09-15
IPC分类号： G11C700
CPC分类号： G11C11/22
摘要： A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.
摘要翻译： 用于1T / 1C铁电存储器阵列的存储单元布局包括具有耦合到字线的栅极和耦合在位线和内部单元节点之间的电流路径的存取晶体管，跨越存储器单元延伸的分流字线 其与存储单元的物理边界内的字线和存取晶体管电隔离，以及耦合在内部单元节点和板线之间的铁电电容器。
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公开(公告)号：US5956266A
公开(公告)日：1999-09-21
申请号：US970452
申请日：1997-11-14
摘要： A reference cell for a 1T/1C ferroelectric memory includes a transistor of a first polarity type having a gate coupled to a reference cell word line, and a current path coupled between a bit line and an internal reference cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line, and a current path coupled between a source of supply voltage and the internal reference cell node, and a ferroelectric capacitor coupled between the internal reference cell node and ground.
摘要翻译： 用于1T / 1C铁电存储器的参考单元包括具有耦合到参考单元字线的栅极和耦合在位线和内部参考单元节点之间的电流通路的第一极性类型的晶体管，第二 具有耦合到预充电线的栅极的极性类型，以及耦合在电源电压源和内部参考单元节点之间的电流路径，以及耦合在内部参考单元节点和地之间的铁电电容器。
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7.发明授权Ferroelectric nonvolatile random access memory utilizing self-bootstrapping plate line segment drivers 失效铁电非易失性随机存取存储器利用自引导板线段驱动器
公开(公告)号：US5598366A
公开(公告)日：1997-01-28
申请号：US515558
申请日：1995-08-16
申请人： William F. Kraus , Dennis R. Wilson
发明人： William F. Kraus , Dennis R. Wilson
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric nonvolatile random access memory array includes multiple ferroelectric memory cells arranged in rows and columns, a word line coupled to a word line input of each of the ferroelectric memory cells in a row, and a bit line coupled to a bit line input of each of the ferroelectric memory cells in a column. The array also includes multiple plate lines, each plate line being arranged into a plurality of plate line segments each coupled to a plate line input of a predetermined number of the ferroelectric memory cells in a row, and multiple NMOS plate line segment drivers coupled to each of the plate line segments for selectively driving the corresponding plate line segment to a full rail voltage. The rows of ferroelectric memory cells and the NMOS plate line segment drivers have substantially the same layout pitch. The plate line segment drivers are each coupled to a center portion of the corresponding plate line segment. Each NMOS plate line segment drivers includes a first NMOS transistor having a first current node coupled to the word line associated with the ferroelectric memory cells coupled to the plate line segment, a gate coupled to a source of supply voltage, and a second current node, and a second NMOS transistor having a first current node coupled to the plate line segment, a second current node coupled to a plate clock line, and a gate coupled to the second current node of the first NMOS transistor.
摘要翻译： 铁电非易失性随机存取存储器阵列包括以行和列排列的多个铁电存储单元，一行耦合到每行一个铁电存储单元的字线输入的字线，以及耦合到每行的一个位线输入的位线 的铁电存储单元。 阵列还包括多个板线，每个板线被布置成多个板线段，每个板线段连接到一行中预定数量的铁电存储器单元的板线输入，以及多个NMOS板线段驱动器，其耦合到每个 的板线段用于选择性地将相应的板线段驱动到满轨电压。 铁电存储单元的行和NMOS板线段驱动器具有基本上相同的布局间距。 板线段驱动器各自耦合到对应的板线段的中心部分。 每个NMOS板线段驱动器包括第一NMOS晶体管，其具有耦合到与耦合到板线段的铁电存储器单元相关联的字线的第一电流节点，耦合到电源电压源的栅极和第二电流节点， 以及第二NMOS晶体管，其具有耦合到所述板线段的第一电流节点，耦合到板时钟线的第二电流节点和耦合到所述第一NMOS晶体管的第二电流节点的栅极。
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公开(公告)号：US5901088A
公开(公告)日：1999-05-04
申请号：US22106
申请日：1998-02-11
申请人： William F. Kraus
发明人： William F. Kraus
CPC分类号： G11C7/065
摘要： A cross-coupled sense amplifier includes a voltage-compensating balancing resistor serially connected between the drain of one of the P-channel transistors in the sense amplifier and the corresponding sensing/bit line node. The value of the balancing resistor is optimized so that the voltage imbalance between the P-channel transistor is minimized and sense amplifier sensitivity is maximized. A balancing resistor can also be placed in the N-channel transistors in the sense amplifier if desired. The balancing resistor in a typical application is about 100 to 200 ohms and fabricated from polysilicon.
摘要翻译： 交叉耦合读出放大器包括串联连接在读出放大器中的一个P沟道晶体管的漏极和对应的感测/位线节点之间的电压补偿平衡电阻器。 平衡电阻的值被优化，使得P沟道晶体管之间的电压不平衡最小化，并且感测放大器的灵敏度最大化。 如果需要，还可以将平衡电阻放置在读出放大器中的N沟道晶体管中。 典型应用中的平衡电阻约为100至200欧姆，由多晶硅制成。
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公开(公告)号：US5804996A
公开(公告)日：1998-09-08
申请号：US799999
申请日：1997-02-13
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , H01L21/822 , H01L27/04
CPC分类号： G01R31/31701 , G01R31/31721
摘要： A test mode circuit for an integrated circuit includes a high voltage detector having an input for receiving a high voltage signal, a Schmitt trigger having an input coupled to the output of the high voltage detector, a latch having an input coupled to the output of the Schmitt trigger and an output for providing a test mode signal in a test operational mode, and additional control circuitry for disabling the high voltage detector and Schmitt trigger so that substantially all of the active current flow in the high voltage detector and Schmitt trigger is eliminated in a normal operational mode. The test mode circuit further includes circuitry for preventing a reset condition in the latch during the test mode until a power-down condition occurs. A glitch filter is also included, which is interposed between the output of the Schmitt trigger and the input to the latch. An integrated circuit pin is coupled to both the test mode circuit and to other circuitry on the integrated circuit not forming part of the test mode circuit.
摘要翻译： 用于集成电路的测试模式电路包括具有用于接收高电压信号的输入的高电压检测器，具有耦合到高电压检测器的输出的输入的施密特触发器，具有耦合到输出的输入的锁存器 施密特触发器和用于在测试操作模式下提供测试模式信号的输出，以及用于禁用高电压检测器和施密特触发器的附加控制电路，使得高电压检测器和施密特触发器中的基本上所有的有功电流都被消除 正常的操作模式。 测试模式电路还包括用于在测试模式期间防止锁存器中的复位状态直到发生掉电状态的电路。 还包括一个毛刺滤波器，该滤波器介于施密特触发器的输出端和锁存器的输入端之间。 集成电路引脚耦合到测试模式电路和不形成测试模式电路的一部分的集成电路上的其他电路。
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公开(公告)号：US6141237A
公开(公告)日：2000-10-31
申请号：US351563
申请日：1999-07-12
申请人： Jarrod Eliason , William F. Kraus
发明人： Jarrod Eliason , William F. Kraus
IPC分类号： G11C11/22 , H01L21/8246 , H01L27/105 , H03K3/356
CPC分类号： G11C11/22
摘要： A non-volatile ferroelectric latch includes a sense amplifier having at least one input/output coupled to a bit-line node, a ferroelectric storage capacitor coupled between a plate-line node and the bit-line node, and a load element coupled to the bit-line node. The sense amplifier further includes a second input/output coupled to a second bit-line node and the latch further includes a second ferroelectric storage capacitor coupled between a second plate-line node and the second bit-sine node, and a second load element coupled to the second bit-line node. The load element includes a dynamic, switched ferroelectric capacitor a static, nonswitched ferroelectric capacitor, a linear capacitor, or even a resistive load.
摘要翻译： 非挥发性铁电锁存器包括读出放大器，其具有耦合到位线节点的至少一个输入/输出，耦合在板状线节点和位线节点之间的铁电存储电容器以及耦合到该位线线路节点的负载元件 位线节点。 感测放大器还包括耦合到第二位线节点的第二输入/输出，并且锁存器还包括耦合在第二板状线节点和第二位正弦节点之间的第二铁电存储电容器，以及耦合到第二负载元件的第二负载元件 到第二位线节点。 负载元件包括动态的，开关的铁电电容器，静态的，非开关的铁电电容器，线性电容器或甚至电阻负载。
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